Patch to let alias analysis know about stack and frame pointer..

Jan Hubicka hubicka@atrey.karlin.mff.cuni.cz
Sun Jul 11 13:49:00 GMT 1999


> 
>   In message <19990419005100.51721@atrey.karlin.mff.cuni.cz>you write:
>   > Hi
>   > This patch tells alias analysis, that memory areas referenced by stack
>   > pointer differs from memory references by arg pointer and base pointer.
> Err, I believe the alias code already knows how to deal with this.
> 
> The argument, frame and stack pointers are distinct base values.  
> base_alias_check should have detected this and indicated that such references
> can not alias each other.
I don't remember to see something like this in the alias code....
> 
> It would help us evaluate the problem if you included a testcase for this
> issue.
What kind of test-case do you want? (I can not imagine any testcase reliably
showing that alias analysis do more aliasing that it ought.)
OK. Let consider following:
test(int a, int b)
{
  asm("":::"bx");
  return a+b;
}
The asm output on new_ia32_branch (I don't have normal cvs tree here) is:
test:
        pushl   %ebp
        movl    %esp, %ebp
        pushl   %ebx
        movl    8(%ebp), %edx
        movl    12(%ebp), %eax
#APP
#NO_APP
        popl    %ebx
        leal    (%eax,%edx), %eax
        movl    %ebp, %esp
        popl    %ebp
        ret
There is IMO incorrect block between pushl ebx and movl 8(%ebp) as can be
seen on haifa output for 386: (where some unit blockage or so ought not to play
any role)
;;      Ready list (t =  1):    27
;;              --> scheduling insn <<<27>>> on unit none
;;              dependences resolved: insn 29 into ready
;;              Ready list after queue_to_ready:    29

;;      Ready list (t =  2):    29
;;              --> scheduling insn <<<29>>> on unit none
;;              dependences resolved: insn 30 into ready
;;              Ready list after queue_to_ready:    30

;;      Ready list (t =  3):    30
;;              --> scheduling insn <<<30>>> on unit none
;;              dependences resolved: insn 6 into ready
;;              dependences resolved: insn 4 into ready
;;              Ready list after queue_to_ready:    4  6
The instruction 6 and 4 are the parameter loads. Insn 30 is:

(insn/f 30 29 31 (set (mem:SI (pre_dec:SI (reg:SI 7 esp)) 0)
        (reg:SI 3 ebx)) 33 {pushsi2} (insn_list:REG_DEP_ANTI 29 (insn_list 27 (nil)))
    (nil))

And they are not dependent on this push (even when it access memory).
With my  patch such pushes can be scheduled together.

Hope this helps,
Honza
> 
> jeff

-- 
                       OK. Lets make a signature file.
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|        Jan Hubicka (Jan Hubi\v{c}ka in TeX) hubicka@freesoft.cz         |
|         Czech free software foundation: http://www.freesoft.cz          |
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