PATCH: don't generate fmpyadd/fmpysub on pa8000
Jerry Quinn
jquinn@nortelnetworks.com
Thu Jul 8 12:17:00 GMT 1999
>> "jeff" == Jeffrey A Law <law@cygnus.com> writes:
jeff> In message <199905311755.NAA00308@wmtl249c.us.nortel.com>you write:
>> This patch prevents the fmpyadd and fmpysub patterns in pa.md from
>> generating these instructions for pa8000's. The previous patch only
>> prevented the more complex search in pa_combine_instructions while
>> allowing simple ones to happen.
>>
>> Changelog entry:
>>
>> Mon May 31 13:46:04 EDT 1999 Jerry Quinn <jquinn@nortelnetworks.com>
>>
>> * pa.md (fmpyadd, fmpysub): Prevent generation of fmpyadd and fmpysub
>> instructions on pa8000 processors.
jeff> I still want to know how these are being generated, because to the best
jeff> of my knowledge there should be no way for the compiler to generate
jeff> these instructions when optimizing for the PA8000.
jeff> Precisely which pass in the compiler introduces these insns? (use -da
jeff> to get the dump files).
jeff> The patterns are totally disabled before reload, so we only have to
jeff> worry about post-reload stuff.
jeff> After reload we run Pass Dump file reload_cse .reload jump flow2 .flow2
jeff> sched2 .sched2 jump machine dependent reorg .mach delay slots .dbr
jeff> peephole assembly code
jeff> I'm not aware of a way for any of those passes to generate these insns
jeff> when we're optimizing for the PA8000.
jeff> You need to track down where these insns are coming from before I can
jeff> decide if your patch is correct or not.
The first patch to prevent generation of fmpyadd/sub stops pa_reorg from
moving instructions around that the pattern in pa.md can merge together. What
I think happened is that if the two instructions naturally are next to each
other, the combination pattern can still fire.
However, I've gone and removed this code and can't reproduce it with the
latest snapshot, so I'll drop it for now unless I see it appear again.
Jerry
--
Jerry Quinn Tel: (514) 761-8737
jquinn@nortelnetworks.com Fax: (514) 761-8505
Speech Recognition Research
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