alpha plum hall fix

Richard Henderson rth@cygnus.com
Thu Jul 1 21:09:00 GMT 1999


The following prevents a bit of bad code generation that shows up
in Plum Hall at -O3 on EV4.

Consider

   (set (reg:DI 1)
	(ashift:DI
	  (reg:DI 2)
	  (minus:DI (const_int 56)
		    (ashift:DI
		      (and:DI
			(plus:DI (reg:DI 1001) (const_int -1))
			(const_int 7))
		      (const_int 3)))))

If operand 2 (reg 1001 here) doesn't get a hardreg, eliminate_regs
will helpfully simplify the (plus ...) expression, yielding an
unrecognizable insn.

The ugly part is that for reasons I never tracked down, we don't
actually _report_ an unrecognizable insn.  Instead, we interpret
a bit of garbage as a register number and print that.

I'm not quite sure why Kenner decided to frame these instructions
in this form -- eliminating the 56/-1 in favour of a 64 makes for
a simpler pattern.  It's also how the Arch Ref Manual describes
the instruction, which makes the 56/-1 choice doubly weird.

Please consider this for the release branch as well.


r~


	* alpha.md (extqh): Define as 64-((R&7)*8) instead of 56-(((R-1)&7)*8).
	(extlh, extwh): Likewise.

Index: config/alpha/alpha.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/alpha/alpha.md,v
retrieving revision 1.80.4.2
diff -c -p -d -r1.80.4.2 alpha.md
*** alpha.md	1999/05/31 15:24:57	1.80.4.2
--- alpha.md	1999/07/02 03:44:09
***************
*** 1522,1531 ****
  			(const_int -8))))
     (set (match_dup 4)
  	(ashift:DI (match_dup 3)
! 		   (minus:DI (const_int 56)
  			     (ashift:DI
! 			      (and:DI (plus:DI (match_dup 2) (const_int -1))
! 				      (const_int 7))
  			      (const_int 3)))))
     (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
  	(ashiftrt:DI (match_dup 4) (const_int 56)))]
--- 1522,1530 ----
  			(const_int -8))))
     (set (match_dup 4)
  	(ashift:DI (match_dup 3)
! 		   (minus:DI (const_int 64)
  			     (ashift:DI
! 			      (and:DI (match_dup 2) (const_int 7))
  			      (const_int 3)))))
     (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
  	(ashiftrt:DI (match_dup 4) (const_int 56)))]
***************
*** 1543,1552 ****
  			(const_int -8))))
     (set (match_dup 4)
  	(ashift:DI (match_dup 3)
! 		   (minus:DI (const_int 56)
  			     (ashift:DI
! 			      (and:DI (plus:DI (match_dup 2) (const_int -1))
! 				      (const_int 7))
  			      (const_int 3)))))
     (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
  	(ashiftrt:DI (match_dup 4) (const_int 48)))]
--- 1542,1550 ----
  			(const_int -8))))
     (set (match_dup 4)
  	(ashift:DI (match_dup 3)
! 		   (minus:DI (const_int 64)
  			     (ashift:DI
! 			      (and:DI (match_dup 2) (const_int 7))
  			      (const_int 3)))))
     (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
  	(ashiftrt:DI (match_dup 4) (const_int 48)))]
***************
*** 1603,1613 ****
    [(set (match_operand:DI 0 "register_operand" "=r")
  	(ashift:DI
  	 (match_operand:DI 1 "reg_or_0_operand" "rJ")
! 	  (minus:DI (const_int 56)
  		    (ashift:DI
  		     (and:DI
! 		      (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
! 			       (const_int -1))
  		      (const_int 7))
  		     (const_int 3)))))]
    ""
--- 1601,1610 ----
    [(set (match_operand:DI 0 "register_operand" "=r")
  	(ashift:DI
  	 (match_operand:DI 1 "reg_or_0_operand" "rJ")
! 	  (minus:DI (const_int 64)
  		    (ashift:DI
  		     (and:DI
! 		      (match_operand:DI 2 "reg_or_8bit_operand" "rI")
  		      (const_int 7))
  		     (const_int 3)))))]
    ""
***************
*** 1619,1629 ****
  	(ashift:DI
  	 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
  		 (const_int 2147483647))
! 	 (minus:DI (const_int 56)
  		    (ashift:DI
  		     (and:DI
! 		      (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
! 			       (const_int -1))
  		      (const_int 7))
  		     (const_int 3)))))]
    ""
--- 1616,1625 ----
  	(ashift:DI
  	 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
  		 (const_int 2147483647))
! 	 (minus:DI (const_int 64)
  		    (ashift:DI
  		     (and:DI
! 		      (match_operand:DI 2 "reg_or_8bit_operand" "rI")
  		      (const_int 7))
  		     (const_int 3)))))]
    ""
***************
*** 1635,1645 ****
  	(ashift:DI
  	 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
  		 (const_int 65535))
! 	 (minus:DI (const_int 56)
  		    (ashift:DI
  		     (and:DI
! 		      (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
! 			       (const_int -1))
  		      (const_int 7))
  		     (const_int 3)))))]
    ""
--- 1631,1640 ----
  	(ashift:DI
  	 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
  		 (const_int 65535))
! 	 (minus:DI (const_int 64)
  		    (ashift:DI
  		     (and:DI
! 		      (match_operand:DI 2 "reg_or_8bit_operand" "rI")
  		      (const_int 7))
  		     (const_int 3)))))]
    ""


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