more 64-bit clean PowerPC port

David Edelsohn dje@watson.ibm.com
Fri Jan 15 22:51:00 GMT 1999


	The following patch should make the PowerPC port 64-bit clean when
targetting PowerPC-32.  The port still is missing PowerPC-64 movdi
splitters when hosted on a 64-bit system; I need to see if there is some
way to integrate that support into the existing patterns instead of
duplicating them.

        * rs6000.h (CONST_OK_FOR_LETTER_P): Do not assume 32-bit CONST_INT.
        * rs6000.c (u_short_cint_operand, add_operand, logical_operand,
        non_add_cint_operand, non_logical_cint_operand): Likewise.
        (get_issue_rate): Add CPU_PPC604E case.
        * rs6000.md (movdi, !TARGET_POWERPC64 splitters): Handle 64-bit hosts.

Index: rs6000.c
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.53
diff -c -p -r1.53 rs6000.c
*** rs6000.c	1999/01/12 11:26:42	1.53
--- rs6000.c	1999/01/15 03:52:53
*************** u_short_cint_operand (op, mode)
*** 507,514 ****
       register rtx op;
       enum machine_mode mode ATTRIBUTE_UNUSED;
  {
!   return ((GET_CODE (op) == CONST_INT
! 	   && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0));
  }
  
  /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field.  */
--- 507,514 ----
       register rtx op;
       enum machine_mode mode ATTRIBUTE_UNUSED;
  {
!   return (GET_CODE (op) == CONST_INT
! 	   && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0);
  }
  
  /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field.  */
*************** add_operand (op, mode)
*** 854,860 ****
      enum machine_mode mode;
  {
    return (reg_or_short_operand (op, mode)
! 	  || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0));
  }
  
  /* Return 1 if OP is a constant but not a valid add_operand.  */
--- 854,861 ----
      enum machine_mode mode;
  {
    return (reg_or_short_operand (op, mode)
! 	  || (GET_CODE (op) == CONST_INT
! 	      && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) == 0));
  }
  
  /* Return 1 if OP is a constant but not a valid add_operand.  */
*************** non_add_cint_operand (op, mode)
*** 866,872 ****
  {
    return (GET_CODE (op) == CONST_INT
  	  && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000
! 	  && (INTVAL (op) & 0xffff) != 0);
  }
  
  /* Return 1 if the operand is a non-special register or a constant that
--- 867,873 ----
  {
    return (GET_CODE (op) == CONST_INT
  	  && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000
! 	  && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) != 0);
  }
  
  /* Return 1 if the operand is a non-special register or a constant that
*************** logical_operand (op, mode)
*** 880,886 ****
    return (gpc_reg_operand (op, mode)
  	  || (GET_CODE (op) == CONST_INT
  	      && ((INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0
! 		  || (INTVAL (op) & 0xffff) == 0)));
  }
  
  /* Return 1 if C is a constant that is not a logical operand (as
--- 881,887 ----
    return (gpc_reg_operand (op, mode)
  	  || (GET_CODE (op) == CONST_INT
  	      && ((INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0
! 		  || (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) == 0)));
  }
  
  /* Return 1 if C is a constant that is not a logical operand (as
*************** non_logical_cint_operand (op, mode)
*** 893,899 ****
  {
    return (GET_CODE (op) == CONST_INT
  	  && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) != 0
! 	  && (INTVAL (op) & 0xffff) != 0);
  }
  
  /* Return 1 if C is a constant that can be encoded in a mask on the
--- 894,900 ----
  {
    return (GET_CODE (op) == CONST_INT
  	  && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) != 0
! 	  && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) != 0);
  }
  
  /* Return 1 if C is a constant that can be encoded in a mask on the
Index: rs6000.h
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.34
diff -c -p -r1.34 rs6000.h
*** rs6000.h	1999/01/12 11:26:44	1.34
--- rs6000.h	1999/01/15 04:01:23
*************** enum reg_class
*** 1075,1081 ****
  
  #define CONST_OK_FOR_LETTER_P(VALUE, C)					\
     ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000	\
!    : (C) == 'J' ? ((VALUE) & 0xffff) == 0				\
     : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0		\
     : (C) == 'L' ? mask_constant (VALUE)					\
     : (C) == 'M' ? (VALUE) > 31						\
--- 1075,1081 ----
  
  #define CONST_OK_FOR_LETTER_P(VALUE, C)					\
     ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000	\
!    : (C) == 'J' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff0000)) == 0	\
     : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0		\
     : (C) == 'L' ? mask_constant (VALUE)					\
     : (C) == 'M' ? (VALUE) > 31						\
Index: rs6000.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.36
retrieving revision 1.37
diff -c -p -r1.36 -r1.37
*** rs6000.md	1999/01/15 19:13:42	1.36
--- rs6000.md	1999/01/15 22:40:34	1.37
***************
*** 6127,6139 ****
  {
    operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
    operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
    operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
  }")
  
  (define_split
    [(set (match_operand:DI 0 "gpc_reg_operand" "")
  	(match_operand:DI 1 "const_double_operand" ""))]
!   "! TARGET_POWERPC64 && reload_completed"
    [(set (match_dup 2) (match_dup 4))
     (set (match_dup 3) (match_dup 5))]
    "
--- 6127,6144 ----
  {
    operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
    operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
+ #if HOST_BITS_PER_WIDE_INT == 32
    operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
+ #else
+   operands[4] = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
+   operands[1] = INTVAL (operands[1]) & 0xffffffff;
+ #endif
  }")
  
  (define_split
    [(set (match_operand:DI 0 "gpc_reg_operand" "")
  	(match_operand:DI 1 "const_double_operand" ""))]
!   "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
    [(set (match_dup 2) (match_dup 4))
     (set (match_dup 3) (match_dup 5))]
    "



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