sparcv9 workaround

Stephen L Moshier moshier@mediaone.net
Sun Jan 3 13:16:00 GMT 1999


This change fixes most of the torture test failures on sparcv9.  The
remaining few failures seem unrelated because they apparently do not
depend on TFmode.

To shut off TFmode, it is necessary to make insn flags like HAVE_movtf
be false.  That is done here by making all TFmode predicates depend on
LONG_DOUBLE_TYPE_SIZE.  A similar set of hooks ought to be installed in
i386 and m68k at some point so that XFmode can be turned off properly
when it is necessary or desirable to do so.

	* gcc/configure (sparcv9): Change float_format to i64, for now.
	  sparc/sol2-sld-64.h (LONG_DOUBLE_TYPE_SIZE) Change to 64, for now.
	  sparc/sparc.md (all TFmode): Enable if LONG_DOUBLE_TYPE_SIZE > 64

*** RCS/configure	Sun Dec 27 03:05:36 1998
--- configure	Sun Jan  3 15:19:21 1999
***************
*** 5177,5183 ****
  		xmake_file=sparc/x-sysv4
  		extra_parts="crt1.o crti.o crtn.o gcrt1.o crtbegin.o crtend.o"
  		fixincludes=fixinc.wrap
! 		float_format=i128
  		if test x${enable_threads} = x ; then
  		    enable_threads=$have_pthread_h
  		    if test x${enable_threads} = x ; then
--- 5177,5184 ----
  		xmake_file=sparc/x-sysv4
  		extra_parts="crt1.o crti.o crtn.o gcrt1.o crtbegin.o crtend.o"
  		fixincludes=fixinc.wrap
! 		#float_format=i128
! 		float_format=i64
  		if test x${enable_threads} = x ; then
  		    enable_threads=$have_pthread_h
  		    if test x${enable_threads} = x ; then
*** RCS/sol2-sld-64.h	Wed Dec 16 16:13:25 1998
--- sol2-sld-64.h	Sun Jan  3 14:39:13 1999
***************
*** 26,32 ****
  #define SPARC_DEFAULT_CMODEL CM_MEDANY
  
  #undef LONG_DOUBLE_TYPE_SIZE
! #define LONG_DOUBLE_TYPE_SIZE 128
  
  #undef ASM_CPU32_DEFAULT_SPEC
  #define ASM_CPU32_DEFAULT_SPEC	""
--- 26,32 ----
  #define SPARC_DEFAULT_CMODEL CM_MEDANY
  
  #undef LONG_DOUBLE_TYPE_SIZE
! #define LONG_DOUBLE_TYPE_SIZE 64
  
  #undef ASM_CPU32_DEFAULT_SPEC
  #define ASM_CPU32_DEFAULT_SPEC	""
*** RCS/sparc.md	Wed Dec 16 16:13:34 1998
--- sparc.md	Sun Jan  3 14:00:20 1999
***************
*** 559,565 ****
    [(set (reg:CCFP 96)
  	(compare:CCFP (match_operand:TF 0 "register_operand" "")
  		      (match_operand:TF 1 "register_operand" "")))]
!   "TARGET_FPU"
    "
  {
    sparc_compare_op0 = operands[0];
--- 559,565 ----
    [(set (reg:CCFP 96)
  	(compare:CCFP (match_operand:TF 0 "register_operand" "")
  		      (match_operand:TF 1 "register_operand" "")))]
!   "TARGET_FPU && LONG_DOUBLE_TYPE_SIZE > 64"
    "
  {
    sparc_compare_op0 = operands[0];
***************
*** 615,621 ****
    [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
  	(compare:CCFPE (match_operand:TF 1 "register_operand" "e")
  		       (match_operand:TF 2 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD"
    "*
  {
    if (TARGET_V9)
--- 615,621 ----
    [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
  	(compare:CCFPE (match_operand:TF 1 "register_operand" "e")
  		       (match_operand:TF 2 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "*
  {
    if (TARGET_V9)
***************
*** 654,660 ****
    [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
  	(compare:CCFP (match_operand:TF 1 "register_operand" "e")
  		      (match_operand:TF 2 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD"
    "*
  {
    if (TARGET_V9)
--- 654,660 ----
    [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
  	(compare:CCFP (match_operand:TF 1 "register_operand" "e")
  		      (match_operand:TF 2 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "*
  {
    if (TARGET_V9)
***************
*** 3300,3306 ****
  (define_expand "movtf"
    [(set (match_operand:TF 0 "general_operand" "")
  	(match_operand:TF 1 "general_operand" ""))]
!   ""
    "
  {
    /* Force TFmode constants into memory. */
--- 3300,3306 ----
  (define_expand "movtf"
    [(set (match_operand:TF 0 "general_operand" "")
  	(match_operand:TF 1 "general_operand" ""))]
!   "LONG_DOUBLE_TYPE_SIZE > 64"
    "
  {
    /* Force TFmode constants into memory. */
***************
*** 3358,3363 ****
--- 3358,3364 ----
  	(match_operand:TF 1 "input_operand"    "o,e,o,U,e,r,o,r"))]
    "TARGET_FPU
     && ! TARGET_ARCH64
+    && LONG_DOUBLE_TYPE_SIZE > 64
     && (register_operand (operands[0], TFmode)
         || register_operand (operands[1], TFmode))"
    "#"
***************
*** 3371,3376 ****
--- 3372,3378 ----
    [(set (match_operand:TF 0 "general_operand" "=U,o,r,r,o")
  	(match_operand:TF 1 "input_operand"    "o,U,r,o,r"))]
    "! TARGET_FPU
+    && LONG_DOUBLE_TYPE_SIZE > 64
     && ! TARGET_ARCH64
     && (register_operand (operands[0], TFmode)
         || register_operand (operands[1], TFmode))"
***************
*** 3386,3391 ****
--- 3388,3394 ----
     && TARGET_ARCH64
     && TARGET_V9
     && TARGET_HARD_QUAD
+    && LONG_DOUBLE_TYPE_SIZE > 64
     && (register_operand (operands[0], TFmode)
         || register_operand (operands[1], TFmode))"
    "@
***************
*** 3406,3411 ****
--- 3409,3415 ----
    "TARGET_FPU
     && TARGET_ARCH64
     && ! TARGET_HARD_QUAD
+    && LONG_DOUBLE_TYPE_SIZE > 64
     && (register_operand (operands[0], TFmode)
         || register_operand (operands[1], TFmode))"
    "#"
***************
*** 3416,3421 ****
--- 3420,3426 ----
          (match_operand:TF 1 "input_operand"    "o,r,r"))]
    "! TARGET_FPU
     && TARGET_ARCH64
+    && LONG_DOUBLE_TYPE_SIZE > 64
     && (register_operand (operands[0], TFmode)
         || register_operand (operands[1], TFmode))"
    "#"
***************
*** 3428,3434 ****
    "reload_completed
     && (! TARGET_ARCH64
         || (TARGET_FPU
!            && ! TARGET_HARD_QUAD))"
    [(clobber (const_int 0))]
    "
  {
--- 3433,3440 ----
    "reload_completed
     && (! TARGET_ARCH64
         || (TARGET_FPU
!            && ! TARGET_HARD_QUAD))
!    && LONG_DOUBLE_TYPE_SIZE > 64"
    [(clobber (const_int 0))]
    "
  {
***************
*** 3467,3473 ****
    [(set (match_operand:TF 0 "register_operand" "")
          (match_operand:TF 1 "memory_operand" ""))]
    "(reload_completed
!     && offsettable_memref_p (operands[1]))"
    [(clobber (const_int 0))]
    "
  {
--- 3473,3480 ----
    [(set (match_operand:TF 0 "register_operand" "")
          (match_operand:TF 1 "memory_operand" ""))]
    "(reload_completed
!     && offsettable_memref_p (operands[1]))
!     && LONG_DOUBLE_TYPE_SIZE > 64"
    [(clobber (const_int 0))]
    "
  {
***************
*** 3500,3506 ****
    [(set (match_operand:TF 0 "memory_operand" "")
  	(match_operand:TF 1 "register_operand" ""))]
    "(reload_completed
!     && offsettable_memref_p (operands[0]))"
    [(clobber (const_int 0))]
    "
  {
--- 3507,3514 ----
    [(set (match_operand:TF 0 "memory_operand" "")
  	(match_operand:TF 1 "register_operand" ""))]
    "(reload_completed
!     && offsettable_memref_p (operands[0]))
!     && LONG_DOUBLE_TYPE_SIZE > 64"
    [(clobber (const_int 0))]
    "
  {
***************
*** 3704,3710 ****
  	(if_then_else:TF (match_operand 1 "comparison_operator" "")
  			 (match_operand:TF 2 "register_operand" "")
  			 (match_operand:TF 3 "register_operand" "")))]
!   "TARGET_V9 && TARGET_FPU"
    "
  {
    enum rtx_code code = GET_CODE (operands[1]);
--- 3712,3718 ----
  	(if_then_else:TF (match_operand 1 "comparison_operator" "")
  			 (match_operand:TF 2 "register_operand" "")
  			 (match_operand:TF 3 "register_operand" "")))]
!   "TARGET_V9 && TARGET_FPU && LONG_DOUBLE_TYPE_SIZE > 64"
    "
  {
    enum rtx_code code = GET_CODE (operands[1]);
***************
*** 3837,3843 ****
  				 (const_int 0)])
                           (match_operand:TF 3 "register_operand" "e,0")
                           (match_operand:TF 4 "register_operand" "0,e")))]
!   "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
    "@
     fmovq%C1\\t%x2, %3, %0
     fmovq%c1\\t%x2, %4, %0"
--- 3845,3851 ----
  				 (const_int 0)])
                           (match_operand:TF 3 "register_operand" "e,0")
                           (match_operand:TF 4 "register_operand" "0,e")))]
!   "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "@
     fmovq%C1\\t%x2, %3, %0
     fmovq%c1\\t%x2, %4, %0"
***************
*** 3950,3956 ****
  				 (const_int 0)])
                           (match_operand:TF 3 "register_operand" "e,0")
                           (match_operand:TF 4 "register_operand" "0,e")))]
!   "TARGET_ARCH64 && TARGET_FPU"
    "@
     fmovrq%D1\\t%2, %3, %0
     fmovrq%d1\\t%2, %4, %0"
--- 3958,3964 ----
  				 (const_int 0)])
                           (match_operand:TF 3 "register_operand" "e,0")
                           (match_operand:TF 4 "register_operand" "0,e")))]
!   "TARGET_ARCH64 && TARGET_FPU && LONG_DOUBLE_TYPE_SIZE > 64"
    "@
     fmovrq%D1\\t%2, %3, %0
     fmovrq%d1\\t%2, %4, %0"
***************
*** 4477,4483 ****
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(float_extend:TF
  	 (match_operand:SF 1 "register_operand" "f")))]
!   "TARGET_FPU && TARGET_HARD_QUAD"
    "fstoq\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
--- 4485,4491 ----
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(float_extend:TF
  	 (match_operand:SF 1 "register_operand" "f")))]
!   "TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "fstoq\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
***************
*** 4486,4492 ****
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(float_extend:TF
  	 (match_operand:DF 1 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD"
    "fdtoq\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
--- 4494,4500 ----
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(float_extend:TF
  	 (match_operand:DF 1 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "fdtoq\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
***************
*** 4504,4510 ****
    [(set (match_operand:SF 0 "register_operand" "=f")
  	(float_truncate:SF
  	 (match_operand:TF 1 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD"
    "fqtos\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
--- 4512,4518 ----
    [(set (match_operand:SF 0 "register_operand" "=f")
  	(float_truncate:SF
  	 (match_operand:TF 1 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "fqtos\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
***************
*** 4513,4519 ****
    [(set (match_operand:DF 0 "register_operand" "=e")
  	(float_truncate:DF
  	 (match_operand:TF 1 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD"
    "fqtod\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
--- 4521,4527 ----
    [(set (match_operand:DF 0 "register_operand" "=e")
  	(float_truncate:DF
  	 (match_operand:TF 1 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "fqtod\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
***************
*** 4539,4545 ****
  (define_insn "floatsitf2"
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(float:TF (match_operand:SI 1 "register_operand" "f")))]
!   "TARGET_FPU && TARGET_HARD_QUAD"
    "fitoq\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
--- 4547,4553 ----
  (define_insn "floatsitf2"
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(float:TF (match_operand:SI 1 "register_operand" "f")))]
!   "TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "fitoq\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
***************
*** 4565,4571 ****
  (define_insn "floatditf2"
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(float:TF (match_operand:DI 1 "register_operand" "e")))]
!   "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
    "fxtoq\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
--- 4573,4579 ----
  (define_insn "floatditf2"
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(float:TF (match_operand:DI 1 "register_operand" "e")))]
!   "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "fxtoq\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
***************
*** 4592,4598 ****
  (define_insn "fix_trunctfsi2"
    [(set (match_operand:SI 0 "register_operand" "=f")
  	(fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
!   "TARGET_FPU && TARGET_HARD_QUAD"
    "fqtoi\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
--- 4600,4606 ----
  (define_insn "fix_trunctfsi2"
    [(set (match_operand:SI 0 "register_operand" "=f")
  	(fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
!   "TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "fqtoi\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
***************
*** 4618,4624 ****
  (define_insn "fix_trunctfdi2"
    [(set (match_operand:DI 0 "register_operand" "=e")
  	(fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
!   "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
    "fqtox\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
--- 4626,4632 ----
  (define_insn "fix_trunctfdi2"
    [(set (match_operand:DI 0 "register_operand" "=e")
  	(fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
!   "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "fqtox\\t%1, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
***************
*** 6501,6507 ****
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(plus:TF (match_operand:TF 1 "register_operand" "e")
  		 (match_operand:TF 2 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD"
    "faddq\\t%1, %2, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
--- 6509,6515 ----
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(plus:TF (match_operand:TF 1 "register_operand" "e")
  		 (match_operand:TF 2 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "faddq\\t%1, %2, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
***************
*** 6528,6534 ****
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(minus:TF (match_operand:TF 1 "register_operand" "e")
  		  (match_operand:TF 2 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD"
    "fsubq\\t%1, %2, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
--- 6536,6542 ----
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(minus:TF (match_operand:TF 1 "register_operand" "e")
  		  (match_operand:TF 2 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "fsubq\\t%1, %2, %0"
    [(set_attr "type" "fp")
     (set_attr "length" "1")])
***************
*** 6555,6561 ****
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(mult:TF (match_operand:TF 1 "register_operand" "e")
  		 (match_operand:TF 2 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD"
    "fmulq\\t%1, %2, %0"
    [(set_attr "type" "fpmul")
     (set_attr "length" "1")])
--- 6563,6569 ----
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(mult:TF (match_operand:TF 1 "register_operand" "e")
  		 (match_operand:TF 2 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "fmulq\\t%1, %2, %0"
    [(set_attr "type" "fpmul")
     (set_attr "length" "1")])
***************
*** 6591,6597 ****
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(mult:TF (float_extend:TF (match_operand:DF 1 "register_operand" "e"))
  		 (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))]
!   "(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD"
    "fdmulq\\t%1, %2, %0"
    [(set_attr "type" "fpmul")
     (set_attr "length" "1")])
--- 6599,6606 ----
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(mult:TF (float_extend:TF (match_operand:DF 1 "register_operand" "e"))
  		 (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))]
!   "(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD
!    && LONG_DOUBLE_TYPE_SIZE > 64"
    "fdmulq\\t%1, %2, %0"
    [(set_attr "type" "fpmul")
     (set_attr "length" "1")])
***************
*** 6601,6607 ****
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(div:TF (match_operand:TF 1 "register_operand" "e")
  		(match_operand:TF 2 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD"
    "fdivq\\t%1, %2, %0"
    [(set_attr "type" "fpdivd")
     (set_attr "length" "1")])
--- 6610,6616 ----
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(div:TF (match_operand:TF 1 "register_operand" "e")
  		(match_operand:TF 2 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "fdivq\\t%1, %2, %0"
    [(set_attr "type" "fpdivd")
     (set_attr "length" "1")])
***************
*** 6627,6641 ****
  (define_expand "negtf2"
    [(set (match_operand:TF 0 "register_operand" "=e,e")
  	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
!   "TARGET_FPU"
    "")
  
  (define_insn "*negtf2_notv9"
    [(set (match_operand:TF 0 "register_operand" "=e,e")
  	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
    ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
!   "TARGET_FPU
!    && ! TARGET_V9"
    "@
    fnegs\\t%0, %0
    #"
--- 6636,6649 ----
  (define_expand "negtf2"
    [(set (match_operand:TF 0 "register_operand" "=e,e")
  	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
!   "TARGET_FPU && LONG_DOUBLE_TYPE_SIZE > 64"
    "")
  
  (define_insn "*negtf2_notv9"
    [(set (match_operand:TF 0 "register_operand" "=e,e")
  	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
    ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
!   "TARGET_FPU && ! TARGET_V9 && LONG_DOUBLE_TYPE_SIZE > 64"
    "@
    fnegs\\t%0, %0
    #"
***************
*** 6647,6652 ****
--- 6655,6661 ----
  	(neg:TF (match_operand:TF 1 "register_operand" "")))]
    "TARGET_FPU
     && ! TARGET_V9
+    && LONG_DOUBLE_TYPE_SIZE > 64
     && reload_completed
     && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
    [(set (match_dup 2) (neg:SF (match_dup 3)))
***************
*** 6667,6673 ****
    [(set (match_operand:TF 0 "register_operand" "=e,e")
  	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
    ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
!   "TARGET_FPU && TARGET_V9"
    "@
    fnegd\\t%0, %0
    #"
--- 6676,6682 ----
    [(set (match_operand:TF 0 "register_operand" "=e,e")
  	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
    ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
!   "TARGET_FPU && TARGET_V9 && LONG_DOUBLE_TYPE_SIZE > 64"
    "@
    fnegd\\t%0, %0
    #"
***************
*** 6679,6684 ****
--- 6688,6694 ----
  	(neg:TF (match_operand:TF 1 "register_operand" "")))]
    "TARGET_FPU
     && TARGET_V9
+    && LONG_DOUBLE_TYPE_SIZE > 64
     && reload_completed
     && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
    [(set (match_dup 2) (neg:DF (match_dup 3)))
***************
*** 6745,6758 ****
  (define_insn "abstf2"
    [(set (match_operand:TF 0 "register_operand" "")
  	(abs:TF (match_operand:TF 1 "register_operand" "")))]
!   "TARGET_FPU"
    "")
  
  (define_insn "*abstf2_notv9"
    [(set (match_operand:TF 0 "register_operand" "=e,e")
  	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
    ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
!   "TARGET_FPU && ! TARGET_V9"
    "@
    fabss\\t%0, %0
    #"
--- 6755,6768 ----
  (define_insn "abstf2"
    [(set (match_operand:TF 0 "register_operand" "")
  	(abs:TF (match_operand:TF 1 "register_operand" "")))]
!   "TARGET_FPU && LONG_DOUBLE_TYPE_SIZE > 64"
    "")
  
  (define_insn "*abstf2_notv9"
    [(set (match_operand:TF 0 "register_operand" "=e,e")
  	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
    ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
!   "TARGET_FPU && ! TARGET_V9 && LONG_DOUBLE_TYPE_SIZE > 64"
    "@
    fabss\\t%0, %0
    #"
***************
*** 6764,6769 ****
--- 6774,6780 ----
  	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
    "TARGET_FPU
     && ! TARGET_V9
+    && LONG_DOUBLE_TYPE_SIZE > 64
     && reload_completed
     && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
    [(set (match_dup 2) (abs:SF (match_dup 3)))
***************
*** 6784,6790 ****
    [(set (match_operand:TF 0 "register_operand" "=e,e")
  	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
    ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
!   "TARGET_FPU && TARGET_V9"
    "@
    fabsd\\t%0, %0
    #"
--- 6795,6801 ----
    [(set (match_operand:TF 0 "register_operand" "=e,e")
  	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
    ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
!   "TARGET_FPU && TARGET_V9 && LONG_DOUBLE_TYPE_SIZE > 64"
    "@
    fabsd\\t%0, %0
    #"
***************
*** 6796,6801 ****
--- 6807,6813 ----
  	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
    "TARGET_FPU
     && TARGET_V9
+    && LONG_DOUBLE_TYPE_SIZE > 64
     && reload_completed
     && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
    [(set (match_dup 2) (abs:DF (match_dup 3)))
***************
*** 6862,6868 ****
  (define_insn "sqrttf2"
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD"
    "fsqrtq\\t%1, %0"
    [(set_attr "type" "fpsqrt")
     (set_attr "length" "1")])
--- 6874,6880 ----
  (define_insn "sqrttf2"
    [(set (match_operand:TF 0 "register_operand" "=e")
  	(sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
!   "TARGET_FPU && TARGET_HARD_QUAD && LONG_DOUBLE_TYPE_SIZE > 64"
    "fsqrtq\\t%1, %0"
    [(set_attr "type" "fpsqrt")
     (set_attr "length" "1")])




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