comments on loop changes

Michael Hayes
Sun Feb 28 18:15:00 GMT 1999

Richard Henderson writes:
 > I replicated your complex losage on the Sparc. 

Ah, I thought this worked OK on the Sparc.  I now understand why you
don't like an address cost based method of choosing givs to combine.

Maybe a simple strategy is not to add the extra_cost for a REG+REG
addressing mode if a REG+DISP cost is no greater than REG+REG.

 > ia32 escaped the fcvadd1 test case with 4(%ebx,%eax,8) sort of
 > addressing.  I believe execution time is nearly gratis on late
 > model chips, but that complex addressing modes may have decoder
 > resource implications.  Something I should check on...

We would probably have heard the squeals before now if this was the
case ;-)


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