rs6000.md using CR as GPR

David Edelsohn dje@watson.ibm.com
Fri Feb 19 12:59:00 GMT 1999


	Some patterns were using the condition register operand as the GPR
operand in the output template.  This includes the ones pointed out in the
earlier patch that we are working to correct and a few additional ones I
noticed while verifying the patch.

David


	* rs6000.md (scc plus eq): Fix output template.
	(scc plus ltu): Fix output template and collapse variants
	correcting early clobber.
	(scc plus geu): Fix output template.
	(scc plus gt): Fix output template.
	(scc plus gtu): Fix output template and collapse variants.

Index: rs6000.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.48
diff -c -p -r1.48 rs6000.md
*** rs6000.md	1999/02/17 11:10:34	1.48
--- rs6000.md	1999/02/19 20:32:21
***************
*** 8724,8730 ****
    ""
    "@
     xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
!    {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
     {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
     {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
     {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
--- 8724,8730 ----
    ""
    "@
     xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
!    {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
     {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
     {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
     {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
***************
*** 8745,8751 ****
    ""
    "@
     xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
!    {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
     {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
     {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
     {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
--- 8745,8751 ----
    ""
    "@
     xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
!    {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
     {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
     {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
     {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
***************
*** 9152,9168 ****
     (set_attr "length" "12")])
  
  (define_insn ""
!   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
! 	(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
! 			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
! 		 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
!    (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
    ""
    "@
    {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
    {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
   [(set_attr "length" "12")])
  
  (define_insn ""
--- 9152,9166 ----
     (set_attr "length" "12")])
  
  (define_insn ""
!   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 	(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
! 			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
! 		 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))
!    (clobber (match_scratch:SI 4 "=&r,&r"))]
    ""
    "@
    {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
    {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
   [(set_attr "length" "12")])
  
  (define_insn ""
***************
*** 9388,9394 ****
    ""
    "@
     {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
!    {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
    [(set_attr "type" "compare")
     (set_attr "length" "8")])
  
--- 9386,9392 ----
    ""
    "@
     {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
!    {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3"
    [(set_attr "type" "compare")
     (set_attr "length" "8")])
  
***************
*** 9510,9516 ****
  	 (const_int 0)))
     (clobber (match_scratch:SI 3 "=&r"))]
    ""
!   "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2"
    [(set_attr "type" "compare")
     (set_attr "length" "12")])
  
--- 9508,9514 ----
  	 (const_int 0)))
     (clobber (match_scratch:SI 3 "=&r"))]
    ""
!   "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2"
    [(set_attr "type" "compare")
     (set_attr "length" "12")])
  
***************
*** 9525,9531 ****
  	(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
     (clobber (match_scratch:SI 3 "=&r"))]
    ""
!   "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2"
    [(set_attr "type" "compare")
     (set_attr "length" "12")])
  
--- 9523,9529 ----
  	(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
     (clobber (match_scratch:SI 3 "=&r"))]
    ""
!   "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2"
    [(set_attr "type" "compare")
     (set_attr "length" "12")])
  
***************
*** 9605,9621 ****
     (set_attr "length" "12")])
  
  (define_insn ""
!   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
! 	(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
! 			 (match_operand:SI 2 "reg_or_short_operand" "I,r,rI"))
! 		 (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))
!    (clobber (match_scratch:SI 4 "=&r,&r,&r"))]
    ""
    "@
     {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
-    {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
     {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
!   [(set_attr "length" "8,12,12")])
  
  (define_insn ""
    [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
--- 9603,9618 ----
     (set_attr "length" "12")])
  
  (define_insn ""
!   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 	(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
! 			 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
! 		 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))
!    (clobber (match_scratch:SI 4 "=&r,&r"))]
    ""
    "@
     {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
     {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
!   [(set_attr "length" "8,12")])
  
  (define_insn ""
    [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
***************
*** 9627,9634 ****
     (clobber (match_scratch:SI 4 "=&r,&r"))]
    ""
    "@
!    {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
!    {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
    [(set_attr "type" "compare")
     (set_attr "length" "8,12")])
  
--- 9624,9631 ----
     (clobber (match_scratch:SI 4 "=&r,&r"))]
    ""
    "@
!    {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
!    {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"
    [(set_attr "type" "compare")
     (set_attr "length" "8,12")])
  


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