mn10200 codegen patch

Jeffrey A Law law@cygnus.com
Wed Feb 10 12:41:00 GMT 1999


This fixes a minor code generation problem on the mn102.  It's similar to
a patch I installed for the mn103 a while back.  Somehow I convinced myself
that the mn102 didn't have these instructions :(

Anyway, operand0 in these instructions is an in/out operand, but wasn't
marked as such (or even as an output operand).  In some cases, reload would
drop the write back to memory if the operands got reloaded because reload
wasn't aware that operand 0 was an in/out operand.

        * mn10200.md (bset, bclr): Operand 0 is a read/write operand.

Index: mn10200.md
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/mn10200/mn10200.md,v
retrieving revision 1.58
diff -c -3 -p -r1.58 mn10200.md
*** mn10200.md	1998/12/16 06:44:02	1.58
--- mn10200.md	1999/02/10 20:35:11
***************
*** 656,662 ****
  ;; These clears a constant set of bits in memory or in a register.
  ;; We must support register destinations to make reload happy.
  (define_insn ""
!   [(set (match_operand:QI 0 "general_operand" "R,d")
  	(subreg:QI
  	  (and:HI (subreg:HI (match_dup 0) 0)
  		  (match_operand 1 "const_int_operand" "")) 0))
--- 656,662 ----
  ;; These clears a constant set of bits in memory or in a register.
  ;; We must support register destinations to make reload happy.
  (define_insn ""
!   [(set (match_operand:QI 0 "general_operand" "+R,d")
  	(subreg:QI
  	  (and:HI (subreg:HI (match_dup 0) 0)
  		  (match_operand 1 "const_int_operand" "")) 0))
***************
*** 669,675 ****
  
  ;; This clears a variable set of bits in memory or in a register.
  (define_insn ""
!   [(set (match_operand:QI 0 "general_operand" "R,d")
  	(subreg:QI
  	  (and:HI (subreg:HI (match_dup 0) 0)
  		  (not:HI (match_operand:HI 1 "general_operand" "d,d"))) 0))
--- 669,675 ----
  
  ;; This clears a variable set of bits in memory or in a register.
  (define_insn ""
!   [(set (match_operand:QI 0 "general_operand" "+R,d")
  	(subreg:QI
  	  (and:HI (subreg:HI (match_dup 0) 0)
  		  (not:HI (match_operand:HI 1 "general_operand" "d,d"))) 0))
***************
*** 681,687 ****
    [(set_attr "cc" "clobber")])
  
  (define_insn ""
!   [(set (match_operand:QI 0 "general_operand" "R,d")
  	(subreg:QI
  	  (and:HI (not:HI (match_operand:HI 1 "general_operand" "d,d"))
  		  (subreg:HI (match_dup 0) 0)) 0))
--- 681,687 ----
    [(set_attr "cc" "clobber")])
  
  (define_insn ""
!   [(set (match_operand:QI 0 "general_operand" "+R,d")
  	(subreg:QI
  	  (and:HI (not:HI (match_operand:HI 1 "general_operand" "d,d"))
  		  (subreg:HI (match_dup 0) 0)) 0))
***************
*** 694,700 ****
  
  ;; These set bits in memory.
  (define_insn ""
!   [(set (match_operand:QI 0 "general_operand" "R,d")
  	(subreg:QI
  	  (ior:HI (subreg:HI (match_dup 0) 0)
  		  (match_operand:HI 1 "general_operand" "d,d")) 0))]
--- 694,700 ----
  
  ;; These set bits in memory.
  (define_insn ""
!   [(set (match_operand:QI 0 "general_operand" "+R,d")
  	(subreg:QI
  	  (ior:HI (subreg:HI (match_dup 0) 0)
  		  (match_operand:HI 1 "general_operand" "d,d")) 0))]
***************
*** 705,715 ****
    [(set_attr "cc" "clobber")])
  
  (define_insn ""
!   [(set (match_operand:QI 0 "general_operand" "R,d")
  	(subreg:QI
  	  (ior:HI (match_operand:HI 1 "general_operand" "d,d")
  		  (subreg:HI (match_dup 0) 0)) 0))]
!   ""
    "@
    bset %1,%0
    or %1,%0"
--- 705,715 ----
    [(set_attr "cc" "clobber")])
  
  (define_insn ""
!   [(set (match_operand:QI 0 "general_operand" "+R,d")
  	(subreg:QI
  	  (ior:HI (match_operand:HI 1 "general_operand" "d,d")
  		  (subreg:HI (match_dup 0) 0)) 0))]
!   "0"
    "@
    bset %1,%0
    or %1,%0"


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