mips16 div_trap patch #3

Gavin Romig-Koch gavin@cygnus.com
Wed Feb 3 13:00:00 GMT 1999


Now that the mips16 div_trap is handling const int zero, this copy to register
is no longer necessary.  Removing it eases the burdon on the optimiser just
a tiny bit, and simplifies unoptimized div-trap code.

                                                  -gavin...

       * config/mips/mips.md ([u]divmodsi4,[u]divmoddi4,[u]divsi3,[u]divdi3,
	[u]modsi3,[u]moddi3) : Don't copy the "zero" argument to a register
       	before calling gen_div_trap.

Index: gcc/config/mips/mips.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/mips/mips.md,v
retrieving revision 1.48
diff -c -r1.48 mips.md
*** gcc/config/mips/mips.md	1999/01/18 09:10:44	1.48
--- gcc/config/mips/mips.md	1999/01/22 13:35:58
***************
*** 2248,2254 ****
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       copy_to_mode_reg (SImode, GEN_INT (0)),
  			       GEN_INT (0x7)));
      }
    if (TARGET_CHECK_RANGE_DIV)
--- 2248,2254 ----
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       GEN_INT (0),
  			       GEN_INT (0x7)));
      }
    if (TARGET_CHECK_RANGE_DIV)
***************
*** 2298,2304 ****
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       copy_to_mode_reg (DImode, GEN_INT (0)),
  			       GEN_INT (0x7)));
      }
    if (TARGET_CHECK_RANGE_DIV)
--- 2298,2304 ----
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       GEN_INT (0),
  			       GEN_INT (0x7)));
      }
    if (TARGET_CHECK_RANGE_DIV)
***************
*** 2348,2354 ****
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       copy_to_mode_reg (SImode, GEN_INT (0)),
  			       GEN_INT (0x7)));
      }
    
--- 2348,2354 ----
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       GEN_INT (0),
  			       GEN_INT (0x7)));
      }
    
***************
*** 2389,2395 ****
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       copy_to_mode_reg (DImode, GEN_INT (0)),
  			       GEN_INT (0x7)));
      }
    
--- 2389,2395 ----
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       GEN_INT (0),
  			       GEN_INT (0x7)));
      }
    
***************
*** 2515,2521 ****
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       copy_to_mode_reg (SImode, GEN_INT (0)),
  			       GEN_INT (0x7)));
      }
    if (TARGET_CHECK_RANGE_DIV)
--- 2516,2522 ----
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       GEN_INT (0),
  			       GEN_INT (0x7)));
      }
    if (TARGET_CHECK_RANGE_DIV)
***************
*** 2558,2564 ****
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       copy_to_mode_reg (DImode, GEN_INT (0)),
  			       GEN_INT (0x7)));
      }
    if (TARGET_CHECK_RANGE_DIV)
--- 2559,2565 ----
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       GEN_INT (0),
  			       GEN_INT (0x7)));
      }
    if (TARGET_CHECK_RANGE_DIV)
***************
*** 2601,2607 ****
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       copy_to_mode_reg (SImode, GEN_INT (0)),
  			       GEN_INT (0x7)));
      }
    if (TARGET_CHECK_RANGE_DIV)
--- 2602,2608 ----
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       GEN_INT (0),
  			       GEN_INT (0x7)));
      }
    if (TARGET_CHECK_RANGE_DIV)
***************
*** 2644,2650 ****
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       copy_to_mode_reg (DImode, GEN_INT (0)),
  			       GEN_INT (0x7)));
      }
    if (TARGET_CHECK_RANGE_DIV)
--- 2645,2651 ----
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       GEN_INT (0),
  			       GEN_INT (0x7)));
      }
    if (TARGET_CHECK_RANGE_DIV)
***************
*** 2687,2693 ****
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       copy_to_mode_reg (SImode, GEN_INT (0)),
  			       GEN_INT (0x7)));
      }
    
--- 2688,2694 ----
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       GEN_INT (0),
  			       GEN_INT (0x7)));
      }
    
***************
*** 2721,2727 ****
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       copy_to_mode_reg (DImode, GEN_INT (0)),
  			       GEN_INT (0x7)));
      }
    
--- 2722,2728 ----
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       GEN_INT (0),
  			       GEN_INT (0x7)));
      }
    
***************
*** 2755,2761 ****
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       copy_to_mode_reg (SImode, GEN_INT (0)),
  			       GEN_INT (0x7)));
      }
    
--- 2756,2762 ----
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       GEN_INT (0),
  			       GEN_INT (0x7)));
      }
    
***************
*** 2789,2795 ****
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       copy_to_mode_reg (DImode, GEN_INT (0)),
  			       GEN_INT (0x7)));
      }
    
--- 2790,2796 ----
    if (!TARGET_NO_CHECK_ZERO_DIV)
      {
        emit_insn (gen_div_trap (operands[2],
! 			       GEN_INT (0),
  			       GEN_INT (0x7)));
      }
    


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