alpha float cvt fix

[Richard Henderson]

A pattern like

	(set (reg:SF 1001)
	     (float:SF (subreg:DI (reg:SI 1002))))

will trip up reload on alpha, and try to make it allocate
stack space after it believes it doesn't need to anymore.

This came up before, I think, and I think I'd meant to track
down what was going wrong in reload before fixing the alpha
back end to only do friendlier no-subregging patterns.  I
don't think I'm going to get around to that anytime soon, so
here's to working around the problem.


r~


        * alpha.c (reg_no_subreg_operand): New function.
        * alpha.h (PREDICATE_CODES): Add it.
        * alpha.md (floatdi?f patterns): Use it for op1.

Index: alpha.c
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/alpha/alpha.c,v
retrieving revision 1.74
diff -c -p -d -r1.74 alpha.c
*** alpha.c	1999/03/02 07:21:44	1.74
--- alpha.c	1999/04/07 10:15:36
*************** reg_not_elim_operand (op, mode)
*** 849,855 ****
    return register_operand (op, mode);
  }
  
! /* Return 1 is OP is a memory location that is not an reference (using
     an AND) to an unaligned location.  Take into account what reload
     will do.  */
  
--- 849,855 ----
    return register_operand (op, mode);
  }
  
! /* Return 1 is OP is a memory location that is not a reference (using
     an AND) to an unaligned location.  Take into account what reload
     will do.  */
  
*************** normal_memory_operand (op, mode)
*** 871,876 ****
--- 871,890 ----
  
    return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) != AND;
  }
+ 
+ /* Accept a register, but not a subreg of any kind.  This allows us to
+    avoid pathological cases in reload wrt data movement common in 
+    int->fp conversion.  */
+ 
+ int
+ reg_no_subreg_operand (op, mode)
+      register rtx op;
+      enum machine_mode mode;
+ {
+   if (GET_CODE (op) == SUBREG)
+     return 0;
+   return register_operand (op, mode);
+ }
  
  /* Return 1 if this function can directly return via $26.  */
  
Index: alpha.h
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/alpha/alpha.h,v
retrieving revision 1.61
diff -c -p -d -r1.61 alpha.h
*** alpha.h	1999/03/17 14:49:22	1.61
--- alpha.h	1999/04/07 10:15:36
*************** do {									\
*** 2321,2327 ****
    {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}},			\
    {"any_memory_operand", {MEM}},					\
    {"hard_fp_register_operand", {SUBREG, REG}},				\
!   {"reg_not_elim_operand", {SUBREG, REG}},
  
  /* Tell collect that the object format is ECOFF.  */
  #define OBJECT_FORMAT_COFF
--- 2321,2328 ----
    {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}},			\
    {"any_memory_operand", {MEM}},					\
    {"hard_fp_register_operand", {SUBREG, REG}},				\
!   {"reg_not_elim_operand", {SUBREG, REG}},				\
!   {"reg_no_subreg_operand", {REG}},
  
  /* Tell collect that the object format is ECOFF.  */
  #define OBJECT_FORMAT_COFF
Index: alpha.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/alpha/alpha.md,v
retrieving revision 1.70
diff -c -p -d -r1.70 alpha.md
*** alpha.md	1999/03/11 14:02:42	1.70
--- alpha.md	1999/04/07 10:15:36
***************
*** 1988,1994 ****
  
  (define_insn ""
    [(set (match_operand:SF 0 "register_operand" "=&f")
! 	(float:SF (match_operand:DI 1 "register_operand" "f")))]
    "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
    "cvtq%,%+%& %1,%0"
    [(set_attr "type" "fadd")
--- 1988,1994 ----
  
  (define_insn ""
    [(set (match_operand:SF 0 "register_operand" "=&f")
! 	(float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
    "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
    "cvtq%,%+%& %1,%0"
    [(set_attr "type" "fadd")
***************
*** 1996,2002 ****
  
  (define_insn "floatdisf2"
    [(set (match_operand:SF 0 "register_operand" "=f")
! 	(float:SF (match_operand:DI 1 "register_operand" "f")))]
    "TARGET_FP"
    "cvtq%,%+%& %1,%0"
    [(set_attr "type" "fadd")
--- 1996,2002 ----
  
  (define_insn "floatdisf2"
    [(set (match_operand:SF 0 "register_operand" "=f")
! 	(float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
    "TARGET_FP"
    "cvtq%,%+%& %1,%0"
    [(set_attr "type" "fadd")
***************
*** 2004,2010 ****
  
  (define_insn ""
    [(set (match_operand:DF 0 "register_operand" "=&f")
! 	(float:DF (match_operand:DI 1 "register_operand" "f")))]
    "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
    "cvtq%-%+%& %1,%0"
    [(set_attr "type" "fadd")
--- 2004,2010 ----
  
  (define_insn ""
    [(set (match_operand:DF 0 "register_operand" "=&f")
! 	(float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
    "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
    "cvtq%-%+%& %1,%0"
    [(set_attr "type" "fadd")
***************
*** 2012,2018 ****
  
  (define_insn "floatdidf2"
    [(set (match_operand:DF 0 "register_operand" "=f")
! 	(float:DF (match_operand:DI 1 "register_operand" "f")))]
    "TARGET_FP"
    "cvtq%-%+%& %1,%0"
    [(set_attr "type" "fadd")
--- 2012,2018 ----
  
  (define_insn "floatdidf2"
    [(set (match_operand:DF 0 "register_operand" "=f")
! 	(float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
    "TARGET_FP"
    "cvtq%-%+%& %1,%0"
    [(set_attr "type" "fadd")