i386.md fixes and cleanups
Jan Hubicka
hubicka@horac.ta.jcu.cz
Thu Oct 29 10:31:00 GMT 1998
Hi
Here I am sending patch with various small cleanups/fixes. (Jeff: note that
I've sent one patch with mov?f splits, please don't miss it. I am very
interested in your opinion).
This patch is expected to fix the fp comparsion bug I've reported few
days ago. Note that after aplying local spiling patches all my testcases
stopped to work (they no longer generates the fld between comparsion and
jump). I've redesigned the fix a bit and I can't test it. So PLEASE
if you have any problems with -mno-ieee-fp, just apply this patch and let
me know the results (both possitive and negative).
If you will apply this patch to older sources, second part (.md) will
reject. Just apply only the first part (i386.c) and edit .md file, search
for ftst patterns and add notice_80387_update_cc() at the beggining.
Rest of patch is not important to for fixing this bug.
I believe this bugfix will work. (the older version worked and this is
just cleanup of previous one). But it ought to be tested.
Another bugfix adds "reload_completed" test to split of DImode logic arithmetic.
When -fschedule-insns is used, this patterns was split before reload what caused
dataflow to think, that register is uninicalized and extend the lifetimes
resulting in ugly code.
I've also changed a bit the predicates in md file. Many places general_operand
was used where nonimmediate_operand or nonmemory_operand is more suitable.
So I've changed that.
I've done the reverse for fp patterns. (changed nonimmediate_operand to
general_operand). This is because fp preffer immediate operands
to be used from memory. So if you want to multiply by two, it is better
to store value 2 into memory and do:
fmul <address of value>.
But with nonimmediate operands two insn (load 2 from memory to register
and multiply) were generated and never combined so resulting code was worse.
I've kept nonimmediate_operand constraints in expands, so first rtl code
contains constants loaded by separate fld. Fld expansions puts constants
to memory, combine combines it and reload uses memory reference.
In case constant is 0 or 1, they are not stored to memory so reload
generates fldz and fld1 insns. Hope this is best possible behaviour.
Hope FP is the only such weird case so my changes in other predicates
will not decrease speed.
I've also removed handling of integer reg<->fp reg conversion cases
in extend?f patterns, because they can be handled nicely by generic
code (reload) and possibly result in better code.
Last small change is that I've added forgotten % to constraints of DI
logical operators.
After this patch I would like to send small patch changing | to || and
then another part containing changes
in instruction selection (some leas, some pentium, i386 and k6 specific
patches). I would like to send patch containing new attributes later,
just to get i386.mds more into sync. Otherwise separating the atributes
should be in fact rewriting them again... OK?
Thu Oct 29 12:27:21 1998 Jan Hubicka <hubicka@freesoft.cz>
* i386.c: Fix fp comparsion bug.
(notice_80387_update_cc): New function
(notice_update_cc): don't reset flags in 387 comparsions.
add support for swap?f patterns
(output_float_compare): call notice_80387_update_cc
* i386.md: Fix some constraints, use more strict predicates.
(mul?f, div?f): use nonimmediate_operand predicate.
(extendsf): remove dead code
(extend?f): remove handling of normal register conversion
(fp patterns): change nonimmediate_operand to general_operand
to let gcc combine operations with constant and then store them
to memory. (avoids extra fld)
(ftst patterns): call notice_80387_update_cc
(anddi3,iordi3,xordi3): add % to constraints
(DI mode logical operator split): do split after reload
*** egcs/gcc/config/i386/orig/i386.c Thu Oct 29 12:13:27 1998
--- egcs/gcc/config/i386/i386.c Thu Oct 29 12:38:28 1998
*************** print_operand_address (file, addr)
*** 3836,3841 ****
--- 3836,3854 ----
}
}
+ /* Set cc_status for 80387 insns. We can't handle that in notice_update_cc
+ complettely, since in some cases flags depends at context. So all fp
+ comparsion insns must handle this manually. */
+
+ void
+ notice_80387_update_cc (exp)
+ rtx exp;
+ {
+ CC_STATUS_INIT;
+ cc_status.flags |= CC_IN_80387;
+ if (0 && TARGET_CMOVE && stack_regs_mentioned_p (XEXP (SET_SRC (XVECEXP (exp, 0, 0)), 1)))
+ cc_status.flags |= CC_FCOMI;
+ }
/* Set the cc_status for the results of an insn whose pattern is EXP.
On the 80386, we assume that only test and compare insns, as well
as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, BSF, ASHIFT,
*************** notice_update_cc (exp)
*** 3962,3981 ****
{
if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
return;
- if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
{
! CC_STATUS_INIT;
! if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
! {
! cc_status.flags |= CC_IN_80387;
! if (0 && TARGET_CMOVE && stack_regs_mentioned_p
! (XEXP (SET_SRC (XVECEXP (exp, 0, 0)), 1)))
! cc_status.flags |= CC_FCOMI;
! }
! else
! cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
! return;
}
CC_STATUS_INIT;
--- 3975,4017 ----
{
if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
return;
+ if (GET_CODE (XVECEXP (exp, 0, 0)) == SET
+ && REG_P(SET_DEST (XVECEXP (exp, 0, 0)))
+ && REG_P(SET_SRC (XVECEXP (exp, 0, 0)))
+ && STACK_REG_P(SET_DEST (XVECEXP (exp, 0, 0)))
+ && STACK_REG_P(SET_SRC (XVECEXP (exp, 0, 0))))
+ {
+ /* fxch insns don't alter CC flags. */
+ if (cc_status.value1
+ && reg_overlap_mentioned_p (SET_DEST (XVECEXP (exp, 0, 0)), cc_status.value1))
+ cc_status.value1 = 0;
+ if (cc_status.value2
+ && reg_overlap_mentioned_p (SET_DEST (XVECEXP (exp, 0, 0)), cc_status.value2))
+ cc_status.value2 = 0;
+ if (cc_status.value1
+ && reg_overlap_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0)), cc_status.value1))
+ cc_status.value1 = 0;
+ if (cc_status.value2
+ && reg_overlap_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0)), cc_status.value2))
+ cc_status.value2 = 0;
+
+ return;
+ }
+
+ if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
{
! if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
! {
! if (!(cc_status.flags & CC_IN_80387))
! notice_80387_update_cc(exp);
! }
! else
! {
! CC_STATUS_INIT;
! cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
! }
! return;
}
CC_STATUS_INIT;
*************** output_float_compare (insn, operands)
*** 4304,4309 ****
--- 4340,4346 ----
int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
rtx tmp;
+ notice_80387_update_cc (PATTERN (insn));
if (0 && TARGET_CMOVE && STACK_REG_P (operands[1]))
{
cc_status.flags |= CC_FCOMI;
*** egcs/gcc/config/i386/orig/i386.md Thu Oct 29 13:27:32 1998
--- egcs/gcc/config/i386/i386.md Thu Oct 29 14:30:23 1998
***************
*** 322,327 ****
--- 322,328 ----
"TARGET_80387 && ! TARGET_IEEE_FP"
"*
{
+ notice_80387_update_cc (PATTERN (insn));
if (! STACK_TOP_P (operands[0]))
abort ();
***************
*** 357,362 ****
--- 358,364 ----
"TARGET_80387 && ! TARGET_IEEE_FP"
"*
{
+ notice_80387_update_cc (PATTERN (insn));
if (! STACK_TOP_P (operands[0]))
abort ();
***************
*** 392,397 ****
--- 394,400 ----
"TARGET_80387 && ! TARGET_IEEE_FP"
"*
{
+ notice_80387_update_cc (PATTERN (insn));
if (! STACK_TOP_P (operands[0]))
abort ();
***************
*** 587,594 ****
(define_insn ""
[(set (cc0)
(match_operator 2 "VOIDmode_compare_op"
! [(match_operand:DF 0 "nonimmediate_operand" "f,fm")
! (match_operand:DF 1 "nonimmediate_operand" "fm,f")]))
(clobber (match_scratch:HI 3 "=a,a"))]
"TARGET_80387
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
--- 590,597 ----
(define_insn ""
[(set (cc0)
(match_operator 2 "VOIDmode_compare_op"
! [(match_operand:DF 0 "general_operand" "f,fm")
! (match_operand:DF 1 "general_operand" "fm,f")]))
(clobber (match_scratch:HI 3 "=a,a"))]
"TARGET_80387
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
***************
*** 622,628 ****
(match_operator 2 "VOIDmode_compare_op"
[(match_operand:DF 0 "register_operand" "f")
(float_extend:DF
! (match_operand:SF 1 "nonimmediate_operand" "fm"))]))
(clobber (match_scratch:HI 3 "=a"))]
"TARGET_80387"
"* return output_float_compare (insn, operands);"
--- 625,631 ----
(match_operator 2 "VOIDmode_compare_op"
[(match_operand:DF 0 "register_operand" "f")
(float_extend:DF
! (match_operand:SF 1 "general_operand" "fm"))]))
(clobber (match_scratch:HI 3 "=a"))]
"TARGET_80387"
"* return output_float_compare (insn, operands);"
***************
*** 632,638 ****
[(set (cc0)
(match_operator 2 "VOIDmode_compare_op"
[(float_extend:DF
! (match_operand:SF 0 "nonimmediate_operand" "fm"))
(match_operand:DF 1 "register_operand" "f")]))
(clobber (match_scratch:HI 3 "=a"))]
"TARGET_80387"
--- 635,641 ----
[(set (cc0)
(match_operator 2 "VOIDmode_compare_op"
[(float_extend:DF
! (match_operand:SF 0 "general_operand" "fm"))
(match_operand:DF 1 "register_operand" "f")]))
(clobber (match_scratch:HI 3 "=a"))]
"TARGET_80387"
***************
*** 644,650 ****
(match_operator 2 "VOIDmode_compare_op"
[(float_extend:DF
(match_operand:SF 0 "register_operand" "f"))
! (match_operand:DF 1 "nonimmediate_operand" "fm")]))
(clobber (match_scratch:HI 3 "=a"))]
"TARGET_80387"
"* return output_float_compare (insn, operands);"
--- 647,653 ----
(match_operator 2 "VOIDmode_compare_op"
[(float_extend:DF
(match_operand:SF 0 "register_operand" "f"))
! (match_operand:DF 1 "general_operand" "fm")]))
(clobber (match_scratch:HI 3 "=a"))]
"TARGET_80387"
"* return output_float_compare (insn, operands);"
***************
*** 682,689 ****
(define_insn "*cmpsf_cc_1"
[(set (cc0)
(match_operator 2 "VOIDmode_compare_op"
! [(match_operand:SF 0 "nonimmediate_operand" "f,fm")
! (match_operand:SF 1 "nonimmediate_operand" "fm,f")]))
(clobber (match_scratch:HI 3 "=a,a"))]
"TARGET_80387
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
--- 685,692 ----
(define_insn "*cmpsf_cc_1"
[(set (cc0)
(match_operator 2 "VOIDmode_compare_op"
! [(match_operand:SF 0 "general_operand" "f,fm")
! (match_operand:SF 1 "general_operand" "fm,f")]))
(clobber (match_scratch:HI 3 "=a,a"))]
"TARGET_80387
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
***************
*** 980,986 ****
;; move to get the address of the symbolic object from the GOT.
(define_expand "movsi"
! [(set (match_operand:SI 0 "general_operand" "")
(match_operand:SI 1 "general_operand" ""))]
""
"
--- 983,989 ----
;; move to get the address of the symbolic object from the GOT.
(define_expand "movsi"
! [(set (match_operand:SI 0 "nonimmediate_operand" "")
(match_operand:SI 1 "general_operand" ""))]
""
"
***************
*** 1003,1009 ****
;; On i486, incl reg is faster than movl $1,reg.
(define_insn ""
! [(set (match_operand:SI 0 "general_operand" "=g,r,r")
(match_operand:SI 1 "general_operand" "rn,i,m"))]
"((!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
|| (GET_CODE (operands[1]) != MEM))
--- 1006,1012 ----
;; On i486, incl reg is faster than movl $1,reg.
(define_insn ""
! [(set (match_operand:SI 0 "nonimmediate_operand" "=g,r,r")
(match_operand:SI 1 "general_operand" "rn,i,m"))]
"((!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
|| (GET_CODE (operands[1]) != MEM))
***************
*** 1041,1047 ****
(set_attr "memory" "*,*,load")])
(define_insn ""
! [(set (match_operand:SI 0 "general_operand" "=g,r")
(match_operand:SI 1 "general_operand" "ri,m"))]
"((!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
|| (GET_CODE (operands[1]) != MEM))
--- 1044,1050 ----
(set_attr "memory" "*,*,load")])
(define_insn ""
! [(set (match_operand:SI 0 "nonimmediate_operand" "=g,r")
(match_operand:SI 1 "general_operand" "ri,m"))]
"((!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
|| (GET_CODE (operands[1]) != MEM))
***************
*** 1091,1097 ****
;; On i486, an incl and movl are both faster than incw and movw.
(define_expand "movhi"
! [(set (match_operand:HI 0 "general_operand" "")
(match_operand:HI 1 "general_operand" ""))]
""
"
--- 1094,1100 ----
;; On i486, an incl and movl are both faster than incw and movw.
(define_expand "movhi"
! [(set (match_operand:HI 0 "nonimmediate_operand" "")
(match_operand:HI 1 "general_operand" ""))]
""
"
***************
*** 1107,1113 ****
}")
(define_insn ""
! [(set (match_operand:HI 0 "general_operand" "=g,r")
(match_operand:HI 1 "general_operand" "ri,m"))]
"(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
"*
--- 1110,1116 ----
}")
(define_insn ""
! [(set (match_operand:HI 0 "nonimmediate_operand" "=g,r")
(match_operand:HI 1 "general_operand" "ri,m"))]
"(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
"*
***************
*** 1155,1161 ****
(set_attr "memory" "*,load")])
(define_expand "movstricthi"
! [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
(match_operand:HI 1 "general_operand" ""))]
""
"
--- 1158,1164 ----
(set_attr "memory" "*,load")])
(define_expand "movstricthi"
! [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
(match_operand:HI 1 "general_operand" ""))]
""
"
***************
*** 1171,1177 ****
}")
(define_insn ""
! [(set (strict_low_part (match_operand:HI 0 "general_operand" "+g,r"))
(match_operand:HI 1 "general_operand" "ri,m"))]
"(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
"*
--- 1174,1180 ----
}")
(define_insn ""
! [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+g,r"))
(match_operand:HI 1 "general_operand" "ri,m"))]
"(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
"*
***************
*** 1225,1231 ****
;; or writes %ah, %bh, %ch, %dh.
(define_expand "movqi"
! [(set (match_operand:QI 0 "general_operand" "")
(match_operand:QI 1 "general_operand" ""))]
""
"
--- 1228,1234 ----
;; or writes %ah, %bh, %ch, %dh.
(define_expand "movqi"
! [(set (match_operand:QI 0 "nonimmediate_operand" "")
(match_operand:QI 1 "general_operand" ""))]
""
"
***************
*** 1287,1293 ****
;; faster.
(define_expand "movstrictqi"
! [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
(match_operand:QI 1 "general_operand" ""))]
""
"
--- 1290,1296 ----
;; faster.
(define_expand "movstrictqi"
! [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
(match_operand:QI 1 "general_operand" ""))]
""
"
***************
*** 1373,1379 ****
"* return AS1 (push%L0,%1);")
(define_expand "movsf"
! [(set (match_operand:SF 0 "general_operand" "")
(match_operand:SF 1 "general_operand" ""))]
""
"
--- 1376,1382 ----
"* return AS1 (push%L0,%1);")
(define_expand "movsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "")
(match_operand:SF 1 "general_operand" ""))]
""
"
***************
*** 1509,1515 ****
"* return output_move_pushmem (operands, insn, GET_MODE_SIZE (DFmode),0,0);")
(define_expand "movdf"
! [(set (match_operand:DF 0 "general_operand" "")
(match_operand:DF 1 "general_operand" ""))]
""
"
--- 1512,1518 ----
"* return output_move_pushmem (operands, insn, GET_MODE_SIZE (DFmode),0,0);")
(define_expand "movdf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "")
(match_operand:DF 1 "general_operand" ""))]
""
"
***************
*** 1646,1652 ****
"* return output_move_pushmem (operands, insn, GET_MODE_SIZE (XFmode),0,0);")
(define_expand "movxf"
! [(set (match_operand:XF 0 "general_operand" "")
(match_operand:XF 1 "general_operand" ""))]
""
"
--- 1649,1655 ----
"* return output_move_pushmem (operands, insn, GET_MODE_SIZE (XFmode),0,0);")
(define_expand "movxf"
! [(set (match_operand:XF 0 "nonimmediate_operand" "")
(match_operand:XF 1 "general_operand" ""))]
""
"
***************
*** 1747,1753 ****
(define_insn ""
[(set (match_operand:DI 0 "push_operand" "=<")
! (match_operand:DI 1 "general_operand" "riF"))]
""
"* return output_move_double (operands);")
--- 1750,1756 ----
(define_insn ""
[(set (match_operand:DI 0 "push_operand" "=<")
! (match_operand:DI 1 "nonmemory_operand" "riF"))]
""
"* return output_move_double (operands);")
***************
*** 1758,1764 ****
"* return output_move_pushmem (operands, insn, GET_MODE_SIZE (DImode),0,0);")
(define_expand "movdi"
! [(set (match_operand:DI 0 "general_operand" "")
(match_operand:DI 1 "general_operand" ""))]
""
"
--- 1761,1767 ----
"* return output_move_pushmem (operands, insn, GET_MODE_SIZE (DImode),0,0);")
(define_expand "movdi"
! [(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
""
"
***************
*** 1774,1780 ****
}")
(define_insn ""
! [(set (match_operand:DI 0 "general_operand" "=g,r")
(match_operand:DI 1 "general_operand" "riF,m"))]
"(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
|| (GET_CODE (operands[1]) != MEM)"
--- 1777,1783 ----
}")
(define_insn ""
! [(set (match_operand:DI 0 "nonimmediate_operand" "=g,r")
(match_operand:DI 1 "general_operand" "riF,m"))]
"(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
|| (GET_CODE (operands[1]) != MEM)"
***************
*** 2023,2029 ****
(define_insn "zero_extendsidi2"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
! (zero_extend:DI (match_operand:SI 1 "general_operand" "0,rm,r")))]
""
"#")
--- 2026,2032 ----
(define_insn "zero_extendsidi2"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
! (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))]
""
"#")
***************
*** 2186,2209 ****
(define_insn "extendsfdf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "=fm,f")
(float_extend:DF
! (match_operand:SF 1 "nonimmediate_operand" "f,fm")))]
"TARGET_80387"
"*
{
int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
- if (NON_STACK_REG_P (operands[1]))
- {
- output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
- RET;
- }
-
- if (NON_STACK_REG_P (operands[0]))
- {
- output_to_reg (operands[0], stack_top_dies, 0);
- RET;
- }
-
if (STACK_TOP_P (operands[0]))
return AS1 (fld%z1,%y1);
--- 2189,2200 ----
(define_insn "extendsfdf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "=fm,f")
(float_extend:DF
! (match_operand:SF 2 "nonimmediate_operand" "f,fm")))]
"TARGET_80387"
"*
{
int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
if (STACK_TOP_P (operands[0]))
return AS1 (fld%z1,%y1);
***************
*** 2219,2244 ****
}")
(define_insn "extenddfxf2"
! [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f,f,!*r")
(float_extend:XF
! (match_operand:DF 1 "nonimmediate_operand" "f,fm,!*r,f")))]
"TARGET_80387"
"*
{
int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
- if (NON_STACK_REG_P (operands[1]))
- {
- output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
- RET;
- }
-
- if (NON_STACK_REG_P (operands[0]))
- {
- output_to_reg (operands[0], stack_top_dies, 0);
- RET;
- }
-
if (STACK_TOP_P (operands[0]))
return AS1 (fld%z1,%y1);
--- 2210,2223 ----
}")
(define_insn "extenddfxf2"
! [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
(float_extend:XF
! (match_operand:DF 1 "nonimmediate_operand" "f,fm")))]
"TARGET_80387"
"*
{
int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
if (STACK_TOP_P (operands[0]))
return AS1 (fld%z1,%y1);
***************
*** 2254,2279 ****
}")
(define_insn "extendsfxf2"
! [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f,f,!*r")
(float_extend:XF
! (match_operand:SF 1 "nonimmediate_operand" "f,fm,!*r,f")))]
"TARGET_80387"
"*
{
int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
- if (NON_STACK_REG_P (operands[1]))
- {
- output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
- RET;
- }
-
- if (NON_STACK_REG_P (operands[0]))
- {
- output_to_reg (operands[0], stack_top_dies, 0);
- RET;
- }
-
if (STACK_TOP_P (operands[0]))
return AS1 (fld%z1,%y1);
--- 2233,2246 ----
}")
(define_insn "extendsfxf2"
! [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
(float_extend:XF
! (match_operand:SF 1 "nonimmediate_operand" "f,fm")))]
"TARGET_80387"
"*
{
int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
if (STACK_TOP_P (operands[0]))
return AS1 (fld%z1,%y1);
***************
*** 2905,2911 ****
[(set_attr "type" "binary")])
(define_insn "adddi3"
! [(set (match_operand:DI 0 "general_operand" "=&r,&ro,!r,o,!&r,!o,!o")
(plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o")
(match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o")))
(clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))]
--- 2872,2878 ----
[(set_attr "type" "binary")])
(define_insn "adddi3"
! [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&ro,!r,o,!&r,!o,!o")
(plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o")
(match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o")))
(clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))]
***************
*** 3082,3088 ****
;; able to handle the operand. But leal always works?
(define_expand "addhi3"
! [(set (match_operand:HI 0 "general_operand" "")
(plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:HI 2 "general_operand" "")))]
""
--- 3049,3055 ----
;; able to handle the operand. But leal always works?
(define_expand "addhi3"
! [(set (match_operand:HI 0 "nonimmediate_operand" "")
(plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:HI 2 "general_operand" "")))]
""
***************
*** 3149,3156 ****
[(set_attr "type" "binary")])
(define_expand "addqi3"
! [(set (match_operand:QI 0 "general_operand" "")
! (plus:QI (match_operand:QI 1 "general_operand" "")
(match_operand:QI 2 "general_operand" "")))]
""
"IX86_EXPAND_BINARY_OPERATOR (PLUS, QImode, operands);")
--- 3116,3123 ----
[(set_attr "type" "binary")])
(define_expand "addqi3"
! [(set (match_operand:QI 0 "nonimmediate_operand" "")
! (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "general_operand" "")))]
""
"IX86_EXPAND_BINARY_OPERATOR (PLUS, QImode, operands);")
***************
*** 3225,3231 ****
;;- subtract instructions
(define_insn "subsidi3"
! [(set (match_operand:DI 0 "general_operand" "=&r,&ro,&r,!&r,o,o,!o")
(minus:DI (match_operand:DI 1 "general_operand" "0iF,0,roiF,roiF,riF,o,o")
(zero_extend:DI (match_operand:SI 2 "general_operand" "o,ri,ri,o,ri,i,r"))))
(clobber (match_scratch:SI 3 "=X,X,X,X,X,&r,&r"))]
--- 3192,3198 ----
;;- subtract instructions
(define_insn "subsidi3"
! [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&ro,&r,!&r,o,o,!o")
(minus:DI (match_operand:DI 1 "general_operand" "0iF,0,roiF,roiF,riF,o,o")
(zero_extend:DI (match_operand:SI 2 "general_operand" "o,ri,ri,o,ri,i,r"))))
(clobber (match_scratch:SI 3 "=X,X,X,X,X,&r,&r"))]
***************
*** 3277,3283 ****
[(set_attr "type" "binary")])
(define_insn "subdi3"
! [(set (match_operand:DI 0 "general_operand" "=&r,&ro,o,o,!&r,!o")
(minus:DI (match_operand:DI 1 "general_operand" "0,0,0iF,or,roiF,roiF")
(match_operand:DI 2 "general_operand" "or,riF,or,iF,roiF,roiF")))
(clobber (match_scratch:SI 3 "=X,X,&r,&r,X,&r"))]
--- 3244,3250 ----
[(set_attr "type" "binary")])
(define_insn "subdi3"
! [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&ro,o,o,!&r,!o")
(minus:DI (match_operand:DI 1 "general_operand" "0,0,0iF,or,roiF,roiF")
(match_operand:DI 2 "general_operand" "or,riF,or,iF,roiF,roiF")))
(clobber (match_scratch:SI 3 "=X,X,&r,&r,X,&r"))]
***************
*** 3364,3370 ****
[(set_attr "type" "binary")])
(define_expand "subhi3"
! [(set (match_operand:HI 0 "general_operand" "")
(minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:HI 2 "general_operand" "")))]
""
--- 3331,3337 ----
[(set_attr "type" "binary")])
(define_expand "subhi3"
! [(set (match_operand:HI 0 "nonimmediate_operand" "")
(minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:HI 2 "general_operand" "")))]
""
***************
*** 3390,3397 ****
[(set_attr "type" "binary")])
(define_expand "subqi3"
! [(set (match_operand:QI 0 "general_operand" "")
! (minus:QI (match_operand:QI 1 "general_operand" "")
(match_operand:QI 2 "general_operand" "")))]
""
"IX86_EXPAND_BINARY_OPERATOR (MINUS, QImode, operands);")
--- 3357,3364 ----
[(set_attr "type" "binary")])
(define_expand "subqi3"
! [(set (match_operand:QI 0 "nonimmediate_operand" "")
! (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "general_operand" "")))]
""
"IX86_EXPAND_BINARY_OPERATOR (MINUS, QImode, operands);")
***************
*** 3531,3544 ****
(define_expand "muldf3"
[(set (match_operand:DF 0 "register_operand" "")
! (mult:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
"TARGET_80387"
"")
(define_expand "mulsf3"
[(set (match_operand:SF 0 "register_operand" "")
! (mult:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
"TARGET_80387"
"")
--- 3498,3511 ----
(define_expand "muldf3"
[(set (match_operand:DF 0 "register_operand" "")
! (mult:DF (match_operand:DF 1 "nonimmediate_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
"TARGET_80387"
"")
(define_expand "mulsf3"
[(set (match_operand:SF 0 "register_operand" "")
! (mult:SF (match_operand:SF 1 "nonimmediate_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
"TARGET_80387"
"")
***************
*** 3571,3584 ****
(define_expand "divdf3"
[(set (match_operand:DF 0 "register_operand" "")
! (div:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
"TARGET_80387"
"")
(define_expand "divsf3"
[(set (match_operand:SF 0 "register_operand" "")
! (div:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
"TARGET_80387"
"")
--- 3538,3551 ----
(define_expand "divdf3"
[(set (match_operand:DF 0 "register_operand" "")
! (div:DF (match_operand:DF 1 "nonimmediate_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
"TARGET_80387"
"")
(define_expand "divsf3"
[(set (match_operand:SF 0 "register_operand" "")
! (div:SF (match_operand:SF 1 "nonimmediate_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
"TARGET_80387"
"")
*************** word_zero_and_operation:
*** 3923,3932 ****
;and we want to and it with memory so we can do this by just an
;andb m,%al and have success.
(define_insn ""
! [(set (match_operand:SI 0 "general_operand" "=r")
(and:SI (zero_extend:SI
(match_operand:HI 1 "nonimmediate_operand" "rm"))
! (match_operand:SI 2 "general_operand" "0")))]
"GET_CODE (operands[2]) == CONST_INT
&& (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))"
"and%W0 %1,%0")
--- 3890,3899 ----
;and we want to and it with memory so we can do this by just an
;andb m,%al and have success.
(define_insn ""
! [(set (match_operand:SI 0 "register_operand" "=r")
(and:SI (zero_extend:SI
(match_operand:HI 1 "nonimmediate_operand" "rm"))
! (match_operand:SI 2 "register_operand" "0")))]
"GET_CODE (operands[2]) == CONST_INT
&& (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))"
"and%W0 %1,%0")
*************** byte_xor_operation:
*** 4290,4297 ****
;; logical operations for DImode
(define_insn "anddi3"
! [(set (match_operand:DI 0 "general_operand" "=&r,&ro")
! (and:DI (match_operand:DI 1 "general_operand" "0,0")
(match_operand:DI 2 "general_operand" "oriF,riF")))]
""
"#"
--- 4257,4264 ----
;; logical operations for DImode
(define_insn "anddi3"
! [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&ro")
! (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "oriF,riF")))]
""
"#"
*************** byte_xor_operation:
*** 4299,4325 ****
(define_insn "iordi3"
! [(set (match_operand:DI 0 "general_operand" "=&r,&ro")
! (ior:DI (match_operand:DI 1 "general_operand" "0,0")
(match_operand:DI 2 "general_operand" "oriF,riF")))]
""
"#"
[(set_attr "type" "binary")])
(define_insn "xordi3"
! [(set (match_operand:DI 0 "general_operand" "=&r,&ro")
! (xor:DI (match_operand:DI 1 "general_operand" "0,0")
(match_operand:DI 2 "general_operand" "oriF,riF")))]
""
"#"
[(set_attr "type" "binary")])
(define_split
! [(set (match_operand:DI 0 "general_operand" "")
(match_operator:DI 3 "ix86_logical_operator"
! [(match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")]))]
! ""
[(set (match_dup 4) (match_op_dup:SI 3 [(match_dup 6) (match_dup 8)]))
(set (match_dup 5) (match_op_dup:SI 3 [(match_dup 7) (match_dup 9)]))]
"split_di (&operands[0], 1, &operands[4], &operands[5]);
--- 4266,4292 ----
(define_insn "iordi3"
! [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&ro")
! (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "oriF,riF")))]
""
"#"
[(set_attr "type" "binary")])
(define_insn "xordi3"
! [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&ro")
! (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "oriF,riF")))]
""
"#"
[(set_attr "type" "binary")])
(define_split
! [(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operator:DI 3 "ix86_logical_operator"
! [(match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "general_operand" "")]))]
! "reload_completed"
[(set (match_dup 4) (match_op_dup:SI 3 [(match_dup 6) (match_dup 8)]))
(set (match_dup 5) (match_op_dup:SI 3 [(match_dup 7) (match_dup 9)]))]
"split_di (&operands[0], 1, &operands[4], &operands[5]);
*************** byte_xor_operation:
*** 6688,6694 ****
;; x86 implementations do this.
(define_expand "ffssi2"
! [(set (match_operand:SI 0 "general_operand" "")
(ffs:SI (match_operand:SI 1 "general_operand" "")))]
""
"
--- 6655,6661 ----
;; x86 implementations do this.
(define_expand "ffssi2"
! [(set (match_operand:SI 0 "nonimmediate_operand" "")
(ffs:SI (match_operand:SI 1 "general_operand" "")))]
""
"
*************** byte_xor_operation:
*** 6715,6721 ****
"* return AS2 (bsf%L0,%1,%0);")
(define_expand "ffshi2"
! [(set (match_operand:SI 0 "general_operand" "")
(ffs:HI (match_operand:HI 1 "general_operand" "")))]
""
"
--- 6682,6688 ----
"* return AS2 (bsf%L0,%1,%0);")
(define_expand "ffshi2"
! [(set (match_operand:SI 0 "nonimmediate_operand" "")
(ffs:HI (match_operand:HI 1 "general_operand" "")))]
""
"
*************** byte_xor_operation:
*** 6752,6759 ****
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_387_op"
! [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
! (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
--- 6719,6726 ----
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_387_op"
! [(match_operand:DF 1 "general_operand" "0,fm")
! (match_operand:DF 2 "general_operand" "fm,0")]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
*************** byte_xor_operation:
*** 6820,6826 ****
(define_insn ""
[(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_387_op"
! [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
(match_operand:XF 2 "register_operand" "0,f")]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
--- 6787,6793 ----
(define_insn ""
[(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_387_op"
! [(float_extend:XF (match_operand:SF 1 "general_operand" "fm,0"))
(match_operand:XF 2 "register_operand" "0,f")]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
*************** byte_xor_operation:
*** 6856,6862 ****
(match_operator:XF 3 "binary_387_op"
[(match_operand:XF 1 "register_operand" "0,f")
(float_extend:XF
! (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
--- 6823,6829 ----
(match_operator:XF 3 "binary_387_op"
[(match_operand:XF 1 "register_operand" "0,f")
(float_extend:XF
! (match_operand:SF 2 "general_operand" "fm,0"))]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
*************** byte_xor_operation:
*** 6872,6878 ****
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_387_op"
! [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
(match_operand:DF 2 "register_operand" "0,f")]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
--- 6839,6845 ----
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_387_op"
! [(float_extend:DF (match_operand:SF 1 "general_operand" "fm,0"))
(match_operand:DF 2 "register_operand" "0,f")]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
*************** byte_xor_operation:
*** 6906,6914 ****
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_387_op"
! [(match_operand:DF 1 "register_operand" "0,f")
(float_extend:DF
! (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
--- 6873,6881 ----
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_387_op"
! [(match_operand:DF 1 "general_operand" "0,fm")
(float_extend:DF
! (match_operand:SF 2 "general_operand" "fm,0"))]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
*************** byte_xor_operation:
*** 6924,6931 ****
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(match_operator:SF 3 "binary_387_op"
! [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
! (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
--- 6891,6898 ----
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(match_operator:SF 3 "binary_387_op"
! [(match_operand:SF 1 "general_operand" "0,fm")
! (match_operand:SF 2 "general_operand" "fm,0")]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
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