PowerPC / rs6000 movsf cleanup
David Edelsohn
dje@watson.ibm.com
Fri Nov 13 20:13:00 GMT 1998
I finally went back and ripped out the lingering movsf
functionality which was explicitly handling moves between GPRs and FPRs
instead of allowing the secondary-reload functionality which was added
since the original machine description. This is the code that already had
to be disabled in PowerPC64 mode and that Kenner had suggested removing a
few months ago. Removing the clutter pointed highlighted some other
strangeness in the remaining code which I cleaned up (nested testing of
TARGET_HARD_FLOAT, duplicate code on SOFT_FLOAT and HARD_FLOAT paths).
Bootstrapping succeeds and no changes in AIX testsuite results. I
remember a comment a few months ago about LinuxPPC problems which were
deferred because we already were planning to update this code. Now is the
chance to see if this addressed that problem.
David
* rs6000.md (movsf): Remove explicit secondary-reload-like
functionality. Only truncate SFmode store if in FPR.
(movsf splitters): Combine const_double splitters.
(movsf_hardfloat): Add GPR support.
Index: rs6000.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.30
retrieving revision 1.31
diff -c -p -r1.30 -r1.31
*** rs6000.md 1998/11/06 13:37:47 1.30
--- rs6000.md 1998/11/13 19:57:13 1.31
***************
*** 5686,5765 ****
&& REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
operands[1] = alter_subreg (operands[1]);
! if (TARGET_SOFT_FLOAT && GET_CODE (operands[0]) == MEM)
! operands[1] = force_reg (SFmode, operands[1]);
!
! else if (TARGET_HARD_FLOAT)
{
! if (! TARGET_POWERPC64
! && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
{
! /* If this is a store to memory or another integer register do the
! move directly. Otherwise store to a temporary stack slot and
! load from there into a floating point register. */
!
! if (GET_CODE (operands[0]) == MEM
! || (GET_CODE (operands[0]) == REG
! && (REGNO (operands[0]) < 32
! || (reload_in_progress
! && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
! {
! emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
! operand_subword (operands[1], 0, 0, SFmode));
! DONE;
! }
! else
! {
! rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
!
! emit_move_insn (stack_slot, operands[1]);
! emit_move_insn (operands[0], stack_slot);
! DONE;
! }
}
-
- if (GET_CODE (operands[0]) == MEM)
- {
- /* If operands[1] is a register, it may have double-precision data
- in it, so truncate it to single precision. We need not do
- this for POWERPC. */
- if (! TARGET_POWERPC && TARGET_HARD_FLOAT
- && GET_CODE (operands[1]) == REG)
- {
- rtx newreg
- = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
- emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
- operands[1] = newreg;
- }
! operands[1] = force_reg (SFmode, operands[1]);
! }
!
! if (! TARGET_POWERPC64
! && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
! {
! if (GET_CODE (operands[1]) == MEM
! #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
! || GET_CODE (operands[1]) == CONST_DOUBLE
! #endif
! || (GET_CODE (operands[1]) == REG
! && (REGNO (operands[1]) < 32
! || (reload_in_progress
! && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))))
! {
! emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
! operand_subword (operands[1], 0, 0, SFmode));
! DONE;
! }
! else
! {
! rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
!
! emit_move_insn (stack_slot, operands[1]);
! emit_move_insn (operands[0], stack_slot);
! DONE;
! }
! }
}
if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT)
--- 5686,5708 ----
&& REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
operands[1] = alter_subreg (operands[1]);
! if (GET_CODE (operands[0]) == MEM)
{
! /* If operands[1] is a register, it may have double-precision data
! in it, so truncate it to single precision. We need not do
! this for POWERPC. */
! if (! TARGET_POWERPC && TARGET_HARD_FLOAT
! && GET_CODE (operands[1]) == REG
! && (FP_REGNO_P (REGNO (operands[1]))
! || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
{
! rtx newreg
! = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
! emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
! operands[1] = newreg;
}
! operands[1] = force_reg (SFmode, operands[1]);
}
if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT)
***************
*** 5775,5781 ****
(define_split
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(match_operand:SF 1 "const_double_operand" ""))]
! "! TARGET_POWERPC64 && reload_completed
&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
|| (GET_CODE (operands[0]) == SUBREG
&& GET_CODE (SUBREG_REG (operands[0])) == REG
--- 5718,5724 ----
(define_split
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(match_operand:SF 1 "const_double_operand" ""))]
! "reload_completed
&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
|| (GET_CODE (operands[0]) == SUBREG
&& GET_CODE (SUBREG_REG (operands[0])) == REG
***************
*** 5789,5832 ****
REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
REAL_VALUE_TO_TARGET_SINGLE (rv, l);
! operands[2] = operand_subword (operands[0], 0, 0, SFmode);
! operands[3] = GEN_INT(l);
! }")
!
! (define_split
! [(set (match_operand:SF 0 "gpc_reg_operand" "")
! (match_operand:SF 1 "const_double_operand" ""))]
! "TARGET_POWERPC64 && reload_completed
! && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
! || (GET_CODE (operands[0]) == SUBREG
! && GET_CODE (SUBREG_REG (operands[0])) == REG
! && REGNO (SUBREG_REG (operands[0])) <= 31))"
! [(set (match_dup 2) (match_dup 3))]
! "
! {
! long l;
! REAL_VALUE_TYPE rv;
!
! REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
! REAL_VALUE_TO_TARGET_SINGLE (rv, l);
- operands[2] = gen_lowpart (SImode, operands[0]);
operands[3] = GEN_INT(l);
}")
(define_insn "*movsf_hardfloat"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,!r,!r")
! (match_operand:SF 1 "input_operand" "f,m,f,G,Fn"))]
"(gpc_reg_operand (operands[0], SFmode)
|| gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
"@
fmr %0,%1
lfs%U1%X1 %0,%1
stfs%U0%X0 %1,%0
#
#"
! [(set_attr "type" "fp,fpload,fpstore,*,*")
! (set_attr "length" "4,4,4,4,8")])
(define_insn "*movsf_softfloat"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
--- 5732,5761 ----
REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
REAL_VALUE_TO_TARGET_SINGLE (rv, l);
! if (! TARGET_POWERPC64)
! operands[2] = operand_subword (operands[0], 0, 0, SFmode);
! else
! operands[2] = gen_lowpart (SImode, operands[0]);
operands[3] = GEN_INT(l);
}")
(define_insn "*movsf_hardfloat"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r")
! (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))]
"(gpc_reg_operand (operands[0], SFmode)
|| gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
"@
+ mr %0,%1
+ {l%U1%X1|lwz%U1%X1} %0,%1
+ {st%U0%X0|stw%U0%X0} %1,%0
fmr %0,%1
lfs%U1%X1 %0,%1
stfs%U0%X0 %1,%0
#
#"
! [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*")
! (set_attr "length" "4,4,4,4,4,4,4,8")])
(define_insn "*movsf_softfloat"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
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