alpha eliminate_regs losage
Richard Henderson
rth@cygnus.com
Fri Nov 6 20:49:00 GMT 1998
On Fri, Nov 06, 1998 at 04:32:44PM -0800, Richard Henderson wrote:
> The following is an attempt to distinguish these two cases, by
> assuming that the load-address sequence described in Kenner's patch
> originally has the form (plus (mult ..) ..).
I somewhat accidentally came across patterns that partially attempted
to address this issue in the alpha md. But they were incomplete and
even when flushed out were not being used because of an optimization
in eliminate_regs_in_insn.
The following works for the test case in question. It isn't quite
optimal, but who cares about this bit of bizzareness. Most importantly,
it is unlikely to break anything else.
It would be good to put this on the egcs-1.1 release branch, as this
came up from someone trying out the prerelease spec99. ;-)
r~
* reload1.c (eliminate_regs_in_insn): Always attempt rerecognition
when eliminiations were done.
* alpha.md (negsi2-*): Update (plus (plus ..) ..) patterns with
more accurate constraints. Add (minus (plus ..) ..) patterns.
Index: reload1.c
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/reload1.c,v
retrieving revision 1.95
diff -c -p -d -r1.95 reload1.c
*** reload1.c 1998/11/06 19:22:36 1.95
--- reload1.c 1998/11/07 04:27:48
*************** eliminate_regs_in_insn (insn, replace)
*** 3317,3322 ****
--- 3317,3334 ----
if (! replace && asm_noperands (old_body) < 0)
new_body = copy_rtx (new_body);
+ #if 1
+ /* ??? A pathological multiply of an eliminated frame pointer needs
+ to be rerecognized here. The below condition is already complex
+ enough, it doesn't seem worth avoiding the validation call. */
+ if (! validate_change (insn, &PATTERN (insn), new_body, 0))
+ {
+ /* If recognition fails, store the new body anyway. It's normal
+ to have recognition failures here due to bizarre memory
+ addresses; reloading will fix them. */
+ PATTERN (insn) = new_body;
+ }
+ #else
/* If we had a move insn but now we don't, rerecognize it. This will
cause spurious re-recognition if the old move had a PARALLEL since
the new one still will, but we can't call single_set without
*************** eliminate_regs_in_insn (insn, replace)
*** 3345,3350 ****
--- 3357,3363 ----
}
else
PATTERN (insn) = new_body;
+ #endif
val = 1;
}
Index: config/alpha/alpha.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/alpha/alpha.md,v
retrieving revision 1.58
diff -c -p -d -r1.58 alpha.md
*** alpha.md 1998/11/06 19:43:53 1.58
--- alpha.md 1998/11/07 04:27:49
***************
*** 611,617 ****
(define_insn ""
[(set (match_operand:DI 0 "some_operand" "=&r")
(plus:DI (plus:DI (match_operand:DI 1 "some_operand" "r")
! (match_operand:DI 2 "some_operand" "r"))
(match_operand:DI 3 "some_operand" "rIOKL")))]
"reload_in_progress"
"#")
--- 611,617 ----
(define_insn ""
[(set (match_operand:DI 0 "some_operand" "=&r")
(plus:DI (plus:DI (match_operand:DI 1 "some_operand" "r")
! (match_operand:DI 2 "some_operand" "rIOKL"))
(match_operand:DI 3 "some_operand" "rIOKL")))]
"reload_in_progress"
"#")
***************
*** 619,636 ****
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:DI 2 "register_operand" ""))
(match_operand:DI 3 "add_operand" "")))]
"reload_completed"
[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
"")
!
(define_insn ""
[(set (match_operand:SI 0 "some_operand" "=&r")
(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ")
(match_operand:SI 2 "const48_operand" "I"))
! (match_operand:SI 3 "some_operand" "r"))
(match_operand:SI 4 "some_operand" "rIOKL")))]
"reload_in_progress"
"#")
--- 619,636 ----
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:DI 2 "add_operand" ""))
(match_operand:DI 3 "add_operand" "")))]
"reload_completed"
[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
"")
!
(define_insn ""
[(set (match_operand:SI 0 "some_operand" "=&r")
(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ")
(match_operand:SI 2 "const48_operand" "I"))
! (match_operand:SI 3 "some_operand" "rIO"))
(match_operand:SI 4 "some_operand" "rIOKL")))]
"reload_in_progress"
"#")
***************
*** 639,646 ****
[(set (match_operand:SI 0 "register_operand" "r")
(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "const48_operand" ""))
! (match_operand:SI 3 "register_operand" ""))
! (match_operand:SI 4 "add_operand" "rIOKL")))]
"reload_completed"
[(set (match_dup 0)
(plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
--- 639,646 ----
[(set (match_operand:SI 0 "register_operand" "r")
(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "const48_operand" ""))
! (match_operand:SI 3 "sext_add_operand" ""))
! (match_operand:SI 4 "add_operand" "")))]
"reload_completed"
[(set (match_dup 0)
(plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
***************
*** 653,660 ****
(plus:SI (plus:SI
(mult:SI (match_operand:SI 1 "some_operand" "rJ")
(match_operand:SI 2 "const48_operand" "I"))
! (match_operand:SI 3 "some_operand" "r"))
! (match_operand:SI 4 "some_operand" "rIOKL"))))]
"reload_in_progress"
"#")
--- 653,660 ----
(plus:SI (plus:SI
(mult:SI (match_operand:SI 1 "some_operand" "rJ")
(match_operand:SI 2 "const48_operand" "I"))
! (match_operand:SI 3 "some_operand" "rIO"))
! (match_operand:SI 4 "some_operand" "rIO"))))]
"reload_in_progress"
"#")
***************
*** 664,698 ****
(plus:SI (plus:SI
(mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "const48_operand" ""))
! (match_operand:SI 3 "register_operand" ""))
! (match_operand:SI 4 "add_operand" ""))))]
"reload_completed"
[(set (match_dup 5)
(plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
! "
! { operands[5] = gen_lowpart (SImode, operands[0]);
! }")
(define_insn ""
[(set (match_operand:DI 0 "some_operand" "=&r")
(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ")
(match_operand:DI 2 "const48_operand" "I"))
! (match_operand:DI 3 "some_operand" "r"))
(match_operand:DI 4 "some_operand" "rIOKL")))]
"reload_in_progress"
"#")
(define_split
! [(set (match_operand:DI 0 "register_operand" "=")
(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "const48_operand" ""))
! (match_operand:DI 3 "register_operand" ""))
(match_operand:DI 4 "add_operand" "")))]
"reload_completed"
[(set (match_dup 0)
(plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
"")
(define_insn "negsi2"
--- 664,781 ----
(plus:SI (plus:SI
(mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "const48_operand" ""))
! (match_operand:SI 3 "sext_add_operand" ""))
! (match_operand:SI 4 "sext_add_operand" ""))))]
"reload_completed"
[(set (match_dup 5)
(plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
! "operands[5] = gen_lowpart (SImode, operands[0]);")
(define_insn ""
[(set (match_operand:DI 0 "some_operand" "=&r")
(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ")
(match_operand:DI 2 "const48_operand" "I"))
! (match_operand:DI 3 "some_operand" "rIO"))
(match_operand:DI 4 "some_operand" "rIOKL")))]
"reload_in_progress"
"#")
(define_split
! [(set (match_operand:DI 0 "register_operand" "")
(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "const48_operand" ""))
! (match_operand:DI 3 "sext_add_operand" ""))
(match_operand:DI 4 "add_operand" "")))]
"reload_completed"
[(set (match_dup 0)
(plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
+ "")
+
+ (define_insn ""
+ [(set (match_operand:DI 0 "some_operand" "=&r")
+ (minus:DI (plus:DI (match_operand:DI 1 "some_operand" "r")
+ (match_operand:DI 2 "some_operand" "rIOKL"))
+ (match_operand:DI 3 "some_operand" "rI")))]
+ "reload_in_progress"
+ "#")
+
+ (define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (minus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "add_operand" ""))
+ (match_operand:DI 3 "reg_or_8bit_operand" "")))]
+ "reload_completed"
+ [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))]
+ "")
+
+ (define_insn ""
+ [(set (match_operand:SI 0 "some_operand" "=&r")
+ (minus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ")
+ (match_operand:SI 2 "const48_operand" "I"))
+ (match_operand:SI 3 "some_operand" "rIO"))
+ (match_operand:SI 4 "some_operand" "rI")))]
+ "reload_in_progress"
+ "#")
+
+ (define_split
+ [(set (match_operand:SI 0 "register_operand" "r")
+ (minus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
+ (match_operand:SI 2 "const48_operand" ""))
+ (match_operand:SI 3 "sext_add_operand" ""))
+ (match_operand:SI 4 "reg_or_8bit_operand" "")))]
+ "reload_completed"
+ [(set (match_dup 0)
+ (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
+ (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 4)))]
+ "")
+
+ (define_insn ""
+ [(set (match_operand:DI 0 "some_operand" "=&r")
+ (sign_extend:DI
+ (minus:SI (plus:SI
+ (mult:SI (match_operand:SI 1 "some_operand" "rJ")
+ (match_operand:SI 2 "const48_operand" "I"))
+ (match_operand:SI 3 "some_operand" "rIO"))
+ (match_operand:SI 4 "some_operand" "rI"))))]
+ "reload_in_progress"
+ "#")
+
+ (define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (sign_extend:DI
+ (minus:SI (plus:SI
+ (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
+ (match_operand:SI 2 "const48_operand" ""))
+ (match_operand:SI 3 "sext_add_operand" ""))
+ (match_operand:SI 4 "reg_or_8bit_operand" ""))))]
+ "reload_completed"
+ [(set (match_dup 5)
+ (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
+ (set (match_dup 0) (sign_extend:DI (minus:SI (match_dup 5) (match_dup 4))))]
+ "operands[5] = gen_lowpart (SImode, operands[0]);")
+
+ (define_insn ""
+ [(set (match_operand:DI 0 "some_operand" "=&r")
+ (minus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ")
+ (match_operand:DI 2 "const48_operand" "I"))
+ (match_operand:DI 3 "some_operand" "rIO"))
+ (match_operand:DI 4 "some_operand" "rI")))]
+ "reload_in_progress"
+ "#")
+
+ (define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (minus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "const48_operand" ""))
+ (match_operand:DI 3 "sext_add_operand" ""))
+ (match_operand:DI 4 "reg_or_8bit_operand" "")))]
+ "reload_completed"
+ [(set (match_dup 0)
+ (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
+ (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 4)))]
"")
(define_insn "negsi2"
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