aarch64: march and mcpu conflict

[Richard Earnshaw]

On 01/09/2026 10:12, Richard Earnshaw (foss) wrote:
> On 29/08/2026 15:46, Christer Solskogen via Gcc-help wrote:
>> After 0188974b4ceaa1f8f3600fec82fdabf7c0ada843 (gcc-16 branch) I get this:
>>
>> gcc -march=native -mcpu=native -E -v - < /dev/null 2>&1 | grep cc1
>>  /usr/lib/gcc/aarch64-unknown-linux-gnu/16/cc1 -E -quiet -v - -mno-fix-cortex-a53-835769 -mno-fix-cortex-a53-843419 -mlittle-endian -mabi=lp64 -march=armv9.2-a+crc+sve2-aes+sve2-bitperm+sve2-sha3+sve2-sm4+nossbs -mcpu=generic-armv8-a+flagm2+lse+dotprod+rdma+crc+fp16fml+jscvt+rcpc2+frintts+i8mm+bf16+sve2-aes+sve2-bitperm+sve2-sha3+sve2-sm4+sb+pauth+wfxt -dumpbase -
>> cc1: warning: switch ‘-mcpu=generic-armv8-a+flagm2+lse+dotprod+rdma+crc+fp16fml+jscvt+rcpc2+frintts+i8mm+bf16+sve2-aes+sve2-bitperm+sve2-sha3+sve2-sm4+sb+pauth+wfxt’ conflicts with ‘-march=armv9.2-a+crc+sve2-aes+sve2-bitperm+sve2-sha3+sve2-sm4+nossbs’ switch and resulted in options ‘+crc+predres+xs’ being added
>>
> 
> If you specify an architecture, you don't need to specify a cpu (though you might want to specify the tuning options with -mtune).  If you specify a CPU, you're specifying both the architecture and the tuning.
> 
> You don't need to specify both the architecture and the CPU - it leads to ambiguities as to what was intended.
> 

I've just noticed this came from using both -mcpu and -march with native.  The behaviour undesirable, but the principle still stands, don't use both options at the same time.

The reason this happens, I think, is that -mcpu looks up the reported CPU id in an internal database, then derives the architecture flags from that.  -march has to work from the list of CPU features reported by the kernel.  If, for some reason, that is not complete there might be a mismatch.

R.

>>
>> Is this really to be expected or is this a bug?
> 
> Yes, it's expected - your cpu specification and architecture specification are in conflict with each other.  GCC has no idea which you intended.
> 
> R.
> 
>>
>> lscpu:
>>
>> Architecture:                aarch64
>>   CPU op-mode(s):            64-bit
>>   Byte Order:                Little Endian
>> CPU(s):                      12
>>   On-line CPU(s) list:       0-11
>> Vendor ID:                   ARM
>>   Model name:                Cortex-A520
>>     Model:                   1
>>     Thread(s) per core:      1
>>     Core(s) per socket:      4
>>     Socket(s):               1
>>     Stepping:                r0p1
>>     Frequency boost:         disabled
>>     CPU(s) scaling MHz:      79%
>>     CPU max MHz:             1800.0000
>>     CPU min MHz:             800.0000
>>     BogoMIPS:                2000.00
>>     Flags:                   fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm sb paca pacg dcpo
>>                              dp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti mte ecv afp mte3 wfxt
>>   Model name:                Cortex-A720
>>     Model:                   1
>>     Thread(s) per core:      1
>>     Core(s) per socket:      8
>>     Socket(s):               1
>>     Stepping:                r0p1
>>     CPU(s) scaling MHz:      52%
>>     CPU max MHz:             2600.0000
>>     CPU min MHz:             800.0000
>>     BogoMIPS:                2000.00
>>     Flags:                   fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm sb paca pacg dcpo
>>                              dp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti mte ecv afp mte3 wfxt
>>
>