GCC veneer code
Wed Aug 2 10:07:34 GMT 2023
I am using gcc-10.2-arm32-eabi with Cortex-R52 processors. The veneer code inserted by the compiler is possibly wrong.
Take IRQ_Handler for example, the veneer code is like below. The first instruction is bx pc, which always switches CPSR to ARM mode. However, my whole project is using Thumb instructions. Can you please help explain how to make the veneer code right, like adding compiler options?
b.n 35811fa0 <__IRQ_Handler_veneer>
ldr pc, [pc, #-4]
this veneer is inserted because of the long distance of the IRQ_handler code.
However, what confuses me is that it also generates the bx instruction, even if with the following related commands:
-mcpu=cortex-r52 ( make sure the CPU is correctly told )
-mthumb ( and there is no -mthumb-interwork )
May I ask more about the documentation problem? Since I found no veneer-related information in the GCC 10.2 Manual, could you please tell me which gcc documents I should refer to?
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