GCC veneer code

Richard Earnshaw (lists) Richard.Earnshaw@arm.com
Tue Aug 1 14:22:35 GMT 2023


On 01/08/2023 11:07, Xingyi Li via Gcc-help wrote:
> Hi,
> I am using gcc-10.2-arm32-eabi with Cortex-R52 processors. The veneer code inserted by the compiler is possibly wrong.
> Take IRQ_Handler for example, the veneer code is like below. The first instruction is bx pc, which always switches CPSR to ARM mode. However, my whole project is using Thumb instructions. Can you please help explain how to make the veneer code right, like adding compiler options?
> 
> <__IRQ_Handler_veneer>:
>    bx pc
>    b.n 35811fa0 <__IRQ_Handler_veneer>
>    ldr pc, [pc, #-4]
>    .word 0x7dac0cfc
> 
> 
> Regards
> XingYi Li(李星毅)
> 

I think this code is being generated by the linker, not the compiler. 
However, since you don't give any details of what commands and options 
you are using to build your code it's very difficult to reason as to 
exactly why this is happening.

In general, veneers are inserted when the linker needs to support 
interworking between Arm and Thumb code or when the target code is 
placed too far away for a direct branch to be used.  This was 
particularly problematic on early versions of the architecture and it 
may be that the linker has not been correctly told that you're using a 
much more recent CPU.

R.


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