Libatomic 16B

[Florian Weimer]

* Satish Vasudeva via Gcc-help:

> I looked into this further. Seems like libat_load_16_i1 is implementing the
> load 16B as "*lock* *cmpxchg16b* (%*rdi*)"
> This is assuming that the CPU doesn't support 16B loads in a single
> transaction. How can I compile libatomics to use intrinsics for load 16B
> instead of LOCK cmpxchg?

As far as I know, it's the only reliable way to implement a 16B load on
x86-64.  The Intel SDM explicitly says this:

| An x87 instruction or an SSE instructions that accesses data larger
| than a quadword may be implemented using multiple memory accesses.

(Section 8.1.1 in Volume 3A in my copy.)

I wish we had a plain 128-bit atomic load instruction, but we don't.

Thanks,
Florian