prevent zero-extension when using a memory load instruction

[Segher Boessenkool]

Hi!

On Mon, Apr 20, 2020 at 10:36:35AM -0400, William Tambe via Gcc-help wrote:
> > > In the machine description file, is there a way to tell GCC that a
> > > memory load instruction already zero-extend such that it does not try
> > > to apply zero-extension ?
> >
> > At least on a load-store architecture (like a usual RISC), you get best
> > results if you make a separate pattern for that, and then let combine
> > combine the zero_extend with the load.
> 
> I tried creating zero_extend pattern that could move data from memory
> to a register (aka memory load), however GCC never used it and
> preferred using memory load followed by a zero-extend.

Use -dap and look at the dump files; see what happened?  You often get
it done by expand already (which isn't such a great idea, but hey), but
some cases are done by combine as well.  If you get separate load and
extend insns generated, you can look at the combine dump to see why
those insns didn't combine there.


Segher