Memory model release/acquire mode interactions of relaxed atomic operations

[Andrew Haley]

On 04/05/17 13:49, Jonathan Wakely wrote:
> On 4 May 2017 at 13:11, Toebs Douglass wrote:
>> This being true if and only if the atomic load/store functions are used,
>> right?  and I suspect those functions are only issuing memory barriers?
>> they do not use atomic operations themselves.  If this is so, then all
>> this is true, but there is within this absolutely no guarantee than any
>> store on any core will ever *actually be seen* by any other core.  If
>> they *are* seen, *they will be in the correct order*, but there is no
>> guarantee they *will* be seen.
> 
> The C++ standard says:
> 
>  An implementation should ensure that the last value (in modification
> order) assigned by an atomic or
> synchronization operation will become visible to all other threads in
> a finite period of time.
> 
> "Should" in ISO-speak is strong encouragement, but not a guarantee.
> However, it is expected that on all but the most esoteric hardware
> platforms it will be true.

It strongly implies that a compiler should not hoist relaxed loads
out of a loop.  Even the most weakly-ordered systems I've used will
eventually pre-empt every core, I suppose, but it can be a long time.

Andrew.