Memory model release/acquire mode interactions of relaxed atomic operations

[Toebs Douglass]

On 05/05/17 10:48, Andrew Haley wrote:
> On 04/05/17 21:18, Toebs Douglass wrote:

>> The problem I have in mind is store buffers and that store barriers do
>> not cause stores to complete. 
> 
> StoreLoad barriers do indeed flush the store buffer.  That's their
> job.  (Or at least they must act as though they do, according to the
> synchronization rules.  I don't know of any processor on which
> StoreLoad doesn't flush the store buffer, but I suppose it's possible
> that somebody could invent another way to do it.)

I may *well* be completely wrong, but looking over the SPARC
architecture manual (I think only the second time I've ever done so, and
I know little otherwise about the architecture), this seems not to be so.

https://cr.yp.to/2005-590/sparcv9.pdf

Section 8.4.3.1 Ordering MEMBAR Instructions (page 150)

This section covers the LoadLoad, StoreLoad, LoadStore and StoreStore
barriers.

"An ordering MEMBAR instruction does not guarantee any completion
property; it only introduces an ordering constraint."

There *are* "sequencing MEMBAR instructions" which *do* control the
completion of operations, but these are different to the load/store type
membars.