best solution for LDRD/STRD/LDM/STM when not 4-byte aligned on aarch32

[Mason]

On 08/03/2017 20:35, Cheryl Edwards (cdedward) wrote:

> ​We have large body of code which we are porting to armv8 chip. The
> application is aarch32 and running on linux. This code works well on
> other processors including x86. We have run across a significant
> number of cases where we are hitting crashes due LDRD/STRD/LDM/STM
> when not 4-byte aligned​. Due to the large amount of code it is
> problematic to find and fix all these cases. Can you provide any
> recommendation on the best way to handle this situation? Thanks in
> advance for any help you can provide.

Hello,

I'd try asking on the Linux ARM mailing list.

linux-arm-kernel@lists.infradead.org

It's mostly used for kernel discussion, but I would venture that
your issue is not a kernel vs user-space issue.

Regards.