is there a way to find the maximum alignment supported by the linker?

[Toby Douglass]

On Mon, Jun 12, 2017 at 1:31 AM, tim prince <n8tm@aol.com> wrote:
> Running in 32-bit mode (should be unusual nowadays) doesn't change cache
> line size or BIOS settings.

Right.

My situation is that I write a library, and it's intended to be
portable, so I'm thinking about every platform which support atomic
instructions, which includes original 32-bit Intel processors.

So I'm not thinking about 32-bit mode on current 64-bit processors -
I'm thinking about actual historical 32-bit prcoessors.

> Turning off adjacent cache line prefetch has been recommended for years when
> running data base or similar server applications.

Makes sense.  What I've read seems to imply it's often ot possible to
do so.  Perhaps it's more commonly offerered as a choice on higher-end
motherboards.  My laptop doesn't seem to have it an as option.

> It could easily be the
> right thing if your application requires one thread to read within 128 bytes
> of where another writes, a potential false sharing case, as well as the data
> base situation where the 2nd cache line is unlikely to be used.

It can be worse than that.  You can have a queue data structure where
there is an enqueue pointer and a dequeue pointer, and they're
independent - but if they're next to each other, every time a thread
enqueues he brings over a copy of the dequeue pointer as well!  this
seemed to cost 30% in performance.

> Also,
> past CPUs fetched cache lines in a variable sequence of 16 byte chunks (but
> always ended up with 64 bytes).

I don't understand this.  Could you explain a bit more?