int64_t divide crashing on cortex-m3

Richard Earnshaw (lists) Richard.Earnshaw@arm.com
Wed Sep 21 16:46:00 GMT 2016


On 21/09/16 17:34, drwho wrote:
> 
> On 2016-09-21 12:18 PM, Richard Earnshaw (lists) wrote:
>> On 21/09/16 17:10, drwho wrote:
>>> Hello,
>>>
>>> I am getting a hard exception fault when doing a divide on a int64_t on
>>> a cortex-m3.  Looking at the lss file, the compiler is doing the int64
>>> divide using __aeabi_ldivmod which uses the instruction movlt.  movlt is
>>> not supported by the cortex-m3.  How do I get gcc to use the right
>>> version of __aeabi_ldivmod?
>>>
>> movlt is perfectly legal on Cortex-m3 in IT blocks.
> Richard, movlt is not listed in the datasheet for the mcu....movt is
> listed on pg76....http://www.atmel.com/images/11011s.pdf

Huh! that document doesn't even go up to page 76.

movlt is a conditional instruction matching mov<c> where <c> == lt (less
than).  The instruction in cortex-m3 is used by prefixing it with an IT
instruction which modifies the behaviour of subsequent instructions.  So

	it lt
	movlt xxxx

is perfectly legal on this processor.

MOVT is a completely different instruction.  It inserts a 16-bit value
in the top half of the destination register, overwriting the previous
bits in that register but leaving the lower half unchanged.

This is all documented in the ARMv7-M version of the ARM ARM
(registration required).

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0403e.b/index.html


R.



> 
> If I change the -march=armv6-m and -mcpu=cortex-m0 the code runs (and
> __aeabi_ldivmod does not contain movlt)
>>
>>> CFLAGS = -MMD -MP -march=armv7-m -mcpu=cortex-m3 -mfix-cortex-m3-ldrd
>>> -mthumb -Wall -O3
>>> LDFLAG = -march=armv7-m -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -mthumb
>>> -nostartfiles -Wl,--no-warn-mismatch -Wl,-dT sam3n.ld
>>>
>> You might want to remove the -Wl,--no-warn-mismatch and check that your
>> input files are correct.  This is a sledgehammer that disables a lot of
>> validation during linking.
> Will do, thanks,
> 
> Jon
> 



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