arm thumb instruction compiled by GCC is not match with spec

[loody]

hi all:
I compile below arm thumb assembly and get binary with gcc version
4.7.1 and version 4.6.3.
with below CFLAGS = "-g -Werror -O1 -mthumb -march='armv7-a' "

    msr cpsr, r0
  26:    f380 8900     msr    CPSR_fc, r0
    msr spsr, r0
  2a:    f390 8900     msr    SPSR_fc, r0

And below is excerpted from ARM arm spec,
DDI0406C_C_arm_architecture_reference_manual.pdf, section A8.8.112
======================================================================
Encoding T1 ARMv6T2, ARMv7
MSR<c> <spec_reg>, <Rn>
======================================================================
15 14 13 12 11 10 9  8  7  6  5  4  3  2  1  0  15 14 13 12 11 10  9
8  7  6  5  4  3  2  1  0
 1   1   1   1   0   0  1  1  1  0  0  0  ---Rn-----   1  0    0   0
mask  0  0  0  0  0  0  0  0  0  0

<spec_reg> Is one of:
• APSR_<bits>
• CPSR_<fields>.
<Rn> Is the ARM core register to be transferred to <spec_reg>.
    <bits> Is one of nzcvq, g, or nzcvqg.
    In the A and R profiles:
    • APSR_nzcvq is the same as CPSR_f
    • APSR_g is the same as CPSR_s
    • APSR_nzcvqg is the same as CPSR_fs.
     <fields> Is a sequence of one or more of the following: s, f.
=========================================================================

My questions are:
1. from arm spec, the binary of "msr cpsr, r0"  should be one of
    a. "0xF380 8c00"
    b. "0xF380 8800"
    c. "0xF380 8400"
    d. "0xF380 8000"
  but why gcc get "0xf380 8900".
  did assembler generate wrong binary?

2. in spec, the <fields> is one or more of "s, f"
    why we get CPSR_fc ?
    is here the "c" the same as "s" in the spec?

Appreciate your kind help in advance,