gcc internal failure during optimization delete_trivially_dead_insns
ftwilliam
ftwilliam@gmail.com
Sat Apr 11 01:41:00 GMT 2015
Hi Jeff,
My apology again; please use instead this patch.
On Fri, Apr 10, 2015 at 7:44 AM, ftwilliam <ftwilliam@gmail.com> wrote:
> Hi Jeff,
>
> I take back some of what I wrote in my previous email.
>
> The issue is reproduceable without binutils, but it will not show up
> during the build.
>
> The following command is to be used from the build directory after
> building has failed:
>
> ./gcc/cc1 -fexceptions /tmp/conftest.c
>
> where the content of /tmp/conftest.c is:
>
> -------------------------------
> void bar ();
> void clean (int *);
> void foo ()
> {
> int i __attribute__ ((cleanup (clean)));
> bar();
> }
> -------------------------------
>
> Please see again attached the patch against trunk.
>
> On Thu, Apr 9, 2015 at 10:21 PM, ftwilliam <ftwilliam@gmail.com> wrote:
>> Hi Jeff,
>>
>> My apologies; I am new to porting GCC; I simply replayed my changed
>> from 4.9.2 and did not recognized the error message as something that
>> I missed.
>>
>> Please see attached the patch against trunk; I used the following when building:
>> ../gcc-repo/configure --prefix=/opt/myarchtoolchain
>> --target=myarch-elf --enable-languages=c
>>
>> The issue is reproduceable only if there is a myarch-elf binutils
>> installed at the --prefix used with ./configure.
>>
>> Renaming the following tools from a different architecture is quick
>> way to reproduce the issue without building a binutils for myarch:
>>
>> myarch-elf-strip
>> myarch-elf-ar
>> myarch-elf-gprof
>> myarch-elf-c++filt
>> myarch-elf-strings
>> myarch-elf-nm
>> myarch-elf-as
>> myarch-elf-elfedit
>> myarch-elf-size
>> myarch-elf-readelf
>> myarch-elf-addr2line
>> myarch-elf-ranlib
>> myarch-elf-objcopy
>> myarch-elf-ld
>> myarch-elf-objdump
>> myarch-elf-ld.bfd
>>
>>
>> On Thu, Apr 9, 2015 at 3:36 PM, Jeff Law <law@redhat.com> wrote:
>>> On 04/08/2015 07:02 AM, ftwilliam wrote:
>>>>
>>>> Hi Jeff,
>>>>
>>>> See attached patch against trunk.
>>>
>>> BTW, when I asked you send the patch along, I assumed that you would have
>>> verified that it was still failing on the trunk.
>>>
>>> jeff
>>>
-------------- next part --------------
diff --git a/config.sub b/config.sub
index 6d2e94c..0854165 100755
--- a/config.sub
+++ b/config.sub
@@ -295,6 +295,7 @@ case $basic_machine in
| moxie \
| mt \
| msp430 \
+ | myarch \
| nds32 | nds32le | nds32be \
| nios | nios2 | nios2eb | nios2el \
| ns16k | ns32k \
diff --git a/configure b/configure
index 064e69b..a87ffe5 100755
--- a/configure
+++ b/configure
@@ -3753,6 +3753,9 @@ case "${target}" in
moxie-*-*)
noconfigdirs="$noconfigdirs gprof"
;;
+ myarch-*-*)
+ noconfigdirs="$noconfigdirs gprof"
+ ;;
h8300*-*-*)
noconfigdirs="$noconfigdirs target-libgloss"
;;
diff --git a/configure.ac b/configure.ac
index 56f6af3..94c14a5 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1100,6 +1100,9 @@ case "${target}" in
moxie-*-*)
noconfigdirs="$noconfigdirs gprof"
;;
+ myarch-*-*)
+ noconfigdirs="$noconfigdirs gprof"
+ ;;
h8300*-*-*)
noconfigdirs="$noconfigdirs target-libgloss"
;;
diff --git a/gcc/config.gcc b/gcc/config.gcc
index cb08a5c..2866fa9 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -417,6 +417,10 @@ mips*-*-*)
extra_headers="loongson.h"
extra_options="${extra_options} g.opt mips/mips-tables.opt"
;;
+myarch*)
+ cpu_type=myarch
+ target_has_targetm_common=no
+ ;;
nds32*)
cpu_type=nds32
extra_headers="nds32_intrinsic.h"
@@ -1205,6 +1209,12 @@ moxie-*-moxiebox*)
tm_file="${tm_file} dbxelf.h elfos.h moxie/moxiebox.h newlib-stdint.h"
tmake_file="${tmake_file} moxie/t-moxiebox"
;;
+myarch-*-elf)
+ gas=yes
+ gnu_ld=yes
+ tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
+ tmake_file="${tmake_file} myarch/t-myarch"
+ ;;
h8300-*-rtems*)
tmake_file="${tmake_file} h8300/t-h8300 h8300/t-rtems"
tm_file="h8300/h8300.h dbxelf.h elfos.h h8300/elf.h h8300/rtems.h rtems.h newlib-stdint.h"
diff --git a/gcc/config/myarch/constraints.md b/gcc/config/myarch/constraints.md
new file mode 100644
index 0000000..5fc471e
--- /dev/null
+++ b/gcc/config/myarch/constraints.md
@@ -0,0 +1,53 @@
+;; MYARCH Constraint definitions.
+;; Copyright (C) 2015 Free Software Foundation, Inc.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; -------------------------------------------------------------------------
+;; Constraints
+;; -------------------------------------------------------------------------
+
+(define_constraint "W"
+ "Register indirect memory operand."
+ (and (match_code "mem")
+ (match_test "REG_P (XEXP (op, 0)) &&
+ REGNO_OK_FOR_BASE_P (REGNO (XEXP (op, 0)))")))
+
+(define_constraint "O"
+ "Constant zero"
+ (and (match_code "const_int")
+ (match_test "ival == 0")))
+
+(define_constraint "Imm8"
+ "8-bits constant"
+ (and (match_code "const_int")
+ (match_test "(ival >= -128 && ival < 0) ||
+ (ival > 0 && ival <= 255)")))
+
+(define_constraint "Im16"
+ "16-bits constant"
+ (and (match_code "const_int")
+ (match_test "(ival >= -32768 && ival <= -129) ||
+ (ival >= 256 && ival <= 65535)")))
+
+(define_constraint "Im32"
+ "32-bits constant"
+ (and (match_code "const_int")
+ (match_test "(ival >= -2147483648 && ival <= -32769) ||
+ (ival >= 65536 && ival <= 4294967295)")))
+
+(define_constraint "S"
+ "Symbol reference"
+ (match_code "symbol_ref"))
diff --git a/gcc/config/myarch/myarch-protos.h b/gcc/config/myarch/myarch-protos.h
new file mode 100644
index 0000000..e69c826
--- /dev/null
+++ b/gcc/config/myarch/myarch-protos.h
@@ -0,0 +1,22 @@
+/* Prototypes functions used in the md file & elsewhere.
+ Copyright (C) 2015 Free Software Foundation, Inc.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+extern void myarch_expand_prologue (void);
+extern void myarch_expand_epilogue (void);
+extern int myarch_initial_elimination_offset (int, int);
+extern void myarch_print_operand (FILE *, rtx, int);
+extern void myarch_print_operand_address (FILE *, rtx);
diff --git a/gcc/config/myarch/myarch.c b/gcc/config/myarch/myarch.c
new file mode 100644
index 0000000..ad8df50
--- /dev/null
+++ b/gcc/config/myarch/myarch.c
@@ -0,0 +1,381 @@
+/* MYARCH Target Code.
+ Copyright (C) 2015 Free Software Foundation, Inc.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "output.h"
+#include "insn-attr.h"
+#include "flags.h"
+#include "recog.h"
+#include "reload.h"
+#include "diagnostic-core.h"
+#include "obstack.h"
+#include "hash-set.h"
+#include "machmode.h"
+#include "vec.h"
+#include "double-int.h"
+#include "input.h"
+#include "alias.h"
+#include "symtab.h"
+#include "wide-int.h"
+#include "inchash.h"
+#include "tree.h"
+#include "stor-layout.h"
+#include "varasm.h"
+#include "calls.h"
+#include "hashtab.h"
+#include "function.h"
+#include "statistics.h"
+#include "real.h"
+#include "fixed-value.h"
+#include "expmed.h"
+#include "dojump.h"
+#include "explow.h"
+#include "emit-rtl.h"
+#include "stmt.h"
+#include "expr.h"
+#include "insn-codes.h"
+#include "optabs.h"
+#include "except.h"
+#include "ggc.h"
+#include "target.h"
+#include "target-def.h"
+#include "tm_p.h"
+#include "langhooks.h"
+#include "dominance.h"
+#include "cfg.h"
+#include "cfgrtl.h"
+#include "cfganal.h"
+#include "lcm.h"
+#include "cfgbuild.h"
+#include "cfgcleanup.h"
+#include "predict.h"
+#include "basic-block.h"
+#include "df.h"
+#include "builtins.h"
+
+#define LOSE_AND_RETURN(msgid, x) \
+ do \
+ { \
+ myarch_operand_lossage (msgid, x); \
+ return; \
+ } while (0)
+
+// TARGET_RETURN_IN_MEMORY worker.
+static bool myarch_return_in_memory (
+ const_tree type,
+ const_tree fntype ATTRIBUTE_UNUSED) {
+
+ const HOST_WIDE_INT size = int_size_in_bytes (type);
+
+ return (size == -1 || size > 2*UNITS_PER_WORD);
+}
+
+// Define how to find the value returned by a function.
+// VALTYPE is the data type of the value (as a tree).
+// If the precise function being called is known,
+// FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
+// We always return values in register %14 for myarch.
+static rtx myarch_function_value (
+ const_tree valtype,
+ const_tree fntype_or_decl ATTRIBUTE_UNUSED,
+ bool outgoing ATTRIBUTE_UNUSED) {
+
+ return gen_rtx_REG (TYPE_MODE(valtype), MYARCH_R14);
+}
+
+// Define how to find the value returned by a library function.
+// We always return values in register %14 for myarch.
+static rtx myarch_libcall_value (
+ enum machine_mode mode,
+ const_rtx fun ATTRIBUTE_UNUSED) {
+
+ return gen_rtx_REG (mode, MYARCH_R14);
+}
+
+// TARGET_FUNCTION_VALUE_REGNO_P worker.
+// We always return values in register %14 for myarch.
+static bool myarch_function_value_regno_p (
+ const unsigned int regno) {
+
+ return (regno == MYARCH_R14);
+}
+
+// Emit an error message when we're in an asm,
+// and a fatal error for "normal" insns.
+// Formatted output isn't easily implemented,
+// since we use output_operand_lossage
+// to output the actual message and
+// handle the categorization of the error.
+static void myarch_operand_lossage (
+ const char *msgid,
+ rtx op) {
+
+ debug_rtx (op);
+
+ output_operand_lossage ("%s", msgid);
+}
+
+// PRINT_OPERAND_ADDRESS worker.
+void myarch_print_operand_address (FILE *file, rtx x) {
+
+ switch (GET_CODE (x)) {
+
+ case REG:
+
+ fprintf (file, "%s", reg_names[REGNO (x)]);
+
+ break;
+
+ default:
+
+ output_addr_const (file, x);
+
+ break;
+ }
+}
+
+// PRINT_OPERAND worker.
+void myarch_print_operand (FILE *file, rtx x, int code) {
+
+ rtx operand = x;
+
+ /* New code entries should just be added to the switch below.
+ If handling is finished, just return. If handling was just
+ a modification of the operand, the modified operand should be
+ put in "operand", and then do a break to let default handling
+ (zero-modifier) output the operand. */
+
+ switch (code) {
+
+ case 0:
+ // No code, print as usual.
+ break;
+
+ default:
+
+ LOSE_AND_RETURN ("invalid operand modifier letter", x);
+ }
+
+ // Print an operand as without a modifier letter.
+ switch (GET_CODE (operand)) {
+
+ case REG:
+
+ if (REGNO (operand) > MYARCH_R15)
+ internal_error ("internal error: bad register: %d",
+ REGNO (operand));
+
+ fprintf (file, "%s", reg_names[REGNO (operand)]);
+
+ return;
+
+ case MEM:
+
+ output_address (XEXP (operand, 0));
+
+ return;
+
+ default:
+ // No need to handle all strange variants,
+ // let output_addr_const do it for us.
+ if (CONSTANT_P (operand)) {
+ output_addr_const (file, operand);
+ return;
+ }
+
+ LOSE_AND_RETURN ("unexpected operand", x);
+ }
+}
+
+// Per-function machine data.
+struct GTY(()) machine_function {
+ // Used in expand_prologue() and expand_epilogue().
+ unsigned size_for_adjusting_sp;
+};
+
+// Zero initialization is OK for all current fields.
+static struct machine_function *myarch_init_machine_status (void) {
+ return ggc_cleared_alloc<machine_function> ();
+}
+
+// TARGET_OPTION_OVERRIDE worker.
+// All this curently does is set init_machine_status.
+static void myarch_option_override (void) {
+ // Set the per-function-data initializer.
+ init_machine_status = myarch_init_machine_status;
+}
+
+// Compute the size of the local area
+// and the size to be adjusted
+// by the prologue and epilogue.
+static void myarch_compute_frame (void) {
+ // For aligning the local variables.
+ int stack_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
+ int padding_locals;
+
+ // Padding needed for each element of the frame.
+ unsigned local_vars_size = get_frame_size ();
+ // Align to the stack alignment.
+ padding_locals = local_vars_size % stack_alignment;
+ if (padding_locals) padding_locals = stack_alignment - padding_locals;
+ local_vars_size += padding_locals;
+
+ cfun->machine->size_for_adjusting_sp = local_vars_size +
+ (ACCUMULATE_OUTGOING_ARGS ? crtl->outgoing_args_size : 0);
+}
+
+void myarch_expand_prologue (void) {
+
+ myarch_compute_frame ();
+
+ if (flag_stack_usage_info)
+ current_function_static_stack_size =
+ cfun->machine->size_for_adjusting_sp;
+
+ if (cfun->machine->size_for_adjusting_sp) {
+
+ rtx insn = emit_insn (
+ gen_subsi3 (
+ stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (cfun->machine->size_for_adjusting_sp)));
+
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
+}
+
+void myarch_expand_epilogue (void) {
+
+ if (cfun->machine->size_for_adjusting_sp) {
+
+ rtx insn = emit_insn (
+ gen_addsi3 (
+ stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (cfun->machine->size_for_adjusting_sp)));
+
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
+
+ emit_jump_insn (gen_returner ());
+}
+
+static rtx myarch_function_arg (
+ cumulative_args_t cum_v,
+ enum machine_mode mode,
+ const_tree type ATTRIBUTE_UNUSED,
+ bool named ATTRIBUTE_UNUSED) {
+
+ return NULL_RTX;
+}
+
+static void myarch_function_arg_advance (
+ cumulative_args_t cum_v,
+ enum machine_mode mode,
+ const_tree type,
+ bool named ATTRIBUTE_UNUSED) {
+
+ CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
+
+ *cum = *cum;
+}
+
+// TARGET_STATIC_CHAIN worker.
+// TODO: Function to revisit ...
+static rtx myarch_static_chain (
+ const_tree ARG_UNUSED (fndecl_or_type),
+ bool incoming_p) {
+
+ rtx addr, mem;
+
+ if (incoming_p) addr = plus_constant (Pmode, arg_pointer_rtx, 2*UNITS_PER_WORD);
+ else addr = plus_constant (Pmode, stack_pointer_rtx, -UNITS_PER_WORD);
+
+ mem = gen_rtx_MEM (Pmode, addr);
+ MEM_NOTRAP_P (mem) = 1;
+
+ return mem;
+}
+
+// TARGET_ASM_TRAMPOLINE_TEMPLATE worker.
+// TODO: Function to revisit ...
+static void myarch_asm_trampoline_template (FILE *f) {
+ fprintf (f, "\tinc %%0, 0 ### trampoline template\n");
+}
+
+// TARGET_TRAMPOLINE_INIT worker.
+// TODO: Function to revisit ...
+static void myarch_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) {
+
+ rtx mem, fnaddr = XEXP (DECL_RTL (fndecl), 0);
+
+ emit_block_move (m_tramp, assemble_trampoline_template (),
+ GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
+
+ mem = adjust_address (m_tramp, SImode, 4);
+ emit_move_insn (mem, chain_value);
+ mem = adjust_address (m_tramp, SImode, 16);
+ emit_move_insn (mem, fnaddr);
+}
+
+// Initialize the GCC target structure.
+
+#undef TARGET_PROMOTE_PROTOTYPES
+#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
+
+#undef TARGET_RETURN_IN_MEMORY
+#define TARGET_RETURN_IN_MEMORY myarch_return_in_memory
+#undef TARGET_MUST_PASS_IN_STACK
+#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
+
+#undef TARGET_FUNCTION_ARG
+#define TARGET_FUNCTION_ARG myarch_function_arg
+#undef TARGET_FUNCTION_ARG_ADVANCE
+#define TARGET_FUNCTION_ARG_ADVANCE myarch_function_arg_advance
+
+/* Define this to return an RTX representing the place where
+a function returns or receives a value of data type RET_TYPE,
+a tree node node representing a data type. */
+#undef TARGET_FUNCTION_VALUE
+#define TARGET_FUNCTION_VALUE myarch_function_value
+#undef TARGET_LIBCALL_VALUE
+#define TARGET_LIBCALL_VALUE myarch_libcall_value
+#undef TARGET_FUNCTION_VALUE_REGNO_P
+#define TARGET_FUNCTION_VALUE_REGNO_P myarch_function_value_regno_p
+
+#undef TARGET_STATIC_CHAIN
+#define TARGET_STATIC_CHAIN myarch_static_chain
+#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
+#define TARGET_ASM_TRAMPOLINE_TEMPLATE myarch_asm_trampoline_template
+#undef TARGET_TRAMPOLINE_INIT
+#define TARGET_TRAMPOLINE_INIT myarch_trampoline_init
+
+#undef TARGET_OPTION_OVERRIDE
+#define TARGET_OPTION_OVERRIDE myarch_option_override
+
+struct gcc_target targetm = TARGET_INITIALIZER;
+
+#include "gt-myarch.h"
diff --git a/gcc/config/myarch/myarch.h b/gcc/config/myarch/myarch.h
new file mode 100644
index 0000000..b1f0560
--- /dev/null
+++ b/gcc/config/myarch/myarch.h
@@ -0,0 +1,408 @@
+/* MYARCH Target Definitions.
+ Copyright (C) 2015 Free Software Foundation, Inc.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef GCC_MYARCH_H
+#define GCC_MYARCH_H
+
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "%{!mno-crt0:crt0%O%s} crti.o%s crtbegin.o%s"
+
+#undef ENDFILE_SPEC
+#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
+
+#undef LIB_SPEC
+#define LIB_SPEC "%{!shared:%{!symbolic:-lc}}"
+
+#undef LINK_SPEC
+#define LINK_SPEC "%{h*} %{v:-V} %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
+
+// Layout of Source Language Data Types.
+
+#define INT_TYPE_SIZE 32
+#define SHORT_TYPE_SIZE 16
+#define LONG_TYPE_SIZE 32
+#define LONG_LONG_TYPE_SIZE 64
+
+#define FLOAT_TYPE_SIZE 32
+#define DOUBLE_TYPE_SIZE 64
+#define LONG_DOUBLE_TYPE_SIZE 64
+
+#define DEFAULT_SIGNED_CHAR 0
+
+#undef SIZE_TYPE
+#define SIZE_TYPE "unsigned int"
+
+#undef PTRDIFF_TYPE
+#define PTRDIFF_TYPE "int"
+
+#undef WCHAR_TYPE
+#define WCHAR_TYPE "unsigned int"
+
+#undef WCHAR_TYPE_SIZE
+#define WCHAR_TYPE_SIZE BITS_PER_WORD
+
+#define REGISTER_NAMES { \
+ "%0", "%1", "%2", "%3", \
+ "%4", "%5", "%6", "%7", \
+ "%8", "%9", "%10", "%11", \
+ "%12", "%13", "%14", "%15" }
+
+#define MYARCH_SP 0
+#define MYARCH_R1 1
+#define MYARCH_R2 2
+#define MYARCH_R3 3
+#define MYARCH_R4 4
+#define MYARCH_R5 5
+#define MYARCH_R6 6
+#define MYARCH_R7 7
+#define MYARCH_R8 8
+#define MYARCH_R9 9
+#define MYARCH_R10 10
+#define MYARCH_R11 11
+#define MYARCH_R12 12
+#define MYARCH_R13 13
+#define MYARCH_R14 14
+#define MYARCH_R15 15
+
+#define FIRST_PSEUDO_REGISTER 16
+
+enum reg_class
+{
+ NO_REGS,
+ GENERAL_REGS,
+ ALL_REGS,
+ LIM_REG_CLASSES
+};
+
+
+#define REG_CLASS_CONTENTS \
+{ { 0x00000000 }, /* Empty */ \
+ { 0x0000FFFF }, /* %0 to %15 */ \
+ { 0x0000FFFF } /* All registers */ \
+}
+
+#define N_REG_CLASSES LIM_REG_CLASSES
+
+#define REG_CLASS_NAMES { \
+ "NO_REGS", \
+ "GENERAL_REGS", \
+ "ALL_REGS" }
+
+#define FIXED_REGISTERS { 1, 0, 0, 0, \
+ 0, 0, 0, 0, \
+ 0, 0, 0, 0, \
+ 0, 0, 0, 1 }
+
+#define CALL_USED_REGISTERS FIXED_REGISTERS
+
+/* A C expression that is nonzero if it is permissible to store a
+value of mode MODE in hard register number REGNO (or in several
+registers starting with that one). All gstore registers are
+equivalent, so we can set this to 1. */
+#define HARD_REGNO_MODE_OK(R,M) 1
+
+// A C expression whose value
+// is a register class containing
+// hard register REGNO.
+#define REGNO_REG_CLASS(R) GENERAL_REGS
+
+// A C expression for the number
+// of consecutive hard registers,
+// starting at register number REGNO,
+// required to hold a value
+// of mode MODE.
+#define HARD_REGNO_NREGS(REGNO, MODE) \
+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
+ / UNITS_PER_WORD)
+
+// A C expression that is nonzero
+// if a value of mode MODE1
+// is accessible in mode MODE2
+// without copying.
+#define MODES_TIEABLE_P(MODE1, MODE2) 1
+
+// The Overall Framework of an Assembler File.
+#define ASM_COMMENT_START "#"
+#define ASM_APP_ON ""
+#define ASM_APP_OFF ""
+
+#define FILE_ASM_OP "\t.file\n"
+
+// Switch to the text or data segment.
+#define TEXT_SECTION_ASM_OP "\t.text"
+#define DATA_SECTION_ASM_OP "\t.data"
+
+// Assembler Commands for Alignment.
+#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
+ fprintf (STREAM, "\t.p2align\t%d\n", POWER);
+
+// A C compound statement to output to
+// stdio stream STREAM the assembler syntax
+// for an instruction operand X.
+#define PRINT_OPERAND(STREAM, X, CODE) myarch_print_operand (STREAM, X, CODE)
+
+#define PRINT_OPERAND_ADDRESS(STREAM, X) myarch_print_operand_address (STREAM, X)
+
+// Output and Generation of Labels.
+#define GLOBAL_ASM_OP "\t.global\t"
+
+// A C type for declaring a variable
+// that is used as the first argument of
+// `FUNCTION_ARG' and other related values.
+#define CUMULATIVE_ARGS unsigned int
+
+/* A C statement for initializing the variable CUM
+for the state at the beginning of the argument list.
+For myarch, all arguments are passed on the stack. */
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) (CUM = 0)
+
+// A C expression that is nonzero
+// if REGNO is the number of
+// a hard register in which function
+// arguments are sometimes passed.
+#define FUNCTION_ARG_REGNO_P(r) 0
+
+/* If defined, the maximum amount of space required
+for outgoing arguments will be computed and placed
+into the variable `current_function_outgoing_args_size'.
+No space will be pushed onto the stack for each call;
+instead, the function prologue should increase
+the stack frame size by this amount. */
+#define ACCUMULATE_OUTGOING_ARGS 1
+
+// How Scalar Function Values Are Returned.
+
+// STACK AND CALLING.
+
+// Define this macro if pushing a word
+// onto the stack moves the stack pointer
+// to a smaller address.
+#define STACK_GROWS_DOWNWARD
+
+#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0
+
+// Offset from the frame pointer
+// to the first local variable slot
+// to be allocated.
+#define STARTING_FRAME_OFFSET 0
+
+// Offset of first parameter from
+// the argument pointer register value.
+#define FIRST_PARM_OFFSET(F) 0
+
+// Define this macro to nonzero value
+// if the addresses of local variable slots
+// are at negative offsets from the frame pointer.
+#define FRAME_GROWS_DOWNWARD 1
+
+// An alias for the machine mode for pointers.
+#define Pmode SImode
+
+// A C expression whose value is RTL
+// representing the location of the incoming
+// return address at the beginning of any function,
+// before the prologue.
+#define INCOMING_RETURN_ADDR_RTX \
+ gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, MYARCH_SP))
+
+// Storage Layout.
+#define BITS_BIG_ENDIAN 0
+#define BYTES_BIG_ENDIAN 0
+#define WORDS_BIG_ENDIAN 0
+
+// Alignment required for a function entry point, in bits.
+#define FUNCTION_BOUNDARY 16
+
+/* Define this macro as a C expression
+which is nonzero if accessing less than
+a word of memory (i.e. a `char' or a `short')
+is no faster than accessing a word of memory. */
+#define SLOW_BYTE_ACCESS 1
+
+/* Number of storage units in a word;
+normally the size of a general-purpose
+register, a power of two from 1 or 8. */
+#define UNITS_PER_WORD 4
+
+/* Define this macro to the minimum alignment
+enforced by hardware for the stack pointer
+on this machine. The definition is a C expression
+for the desired alignment (measured in bits). */
+#define STACK_BOUNDARY 32
+
+/* Normal alignment required for function parameters
+on the stack, in bits. All stack parameters receive
+at least this much alignment regardless of data type. */
+#define PARM_BOUNDARY 32
+
+// Alignment of field after `int : 0' in a structure.
+#define EMPTY_FIELD_BOUNDARY 32
+
+// No data type wants to be aligned rounder than this.
+#define BIGGEST_ALIGNMENT 32
+
+// The best alignment to use in cases where we have a choice.
+#define FASTEST_ALIGNMENT 32
+
+// Every structures size must be a multiple of 8 bits.
+#define STRUCTURE_SIZE_BOUNDARY 8
+
+/* Look at the fundamental type that
+is used for a bit-field and use that
+to impose alignment on the enclosing structure.
+struct s {int a:8}; should have same alignment
+as "int", not "char". */
+#define PCC_BITFIELD_TYPE_MATTERS 1
+
+// Largest integer machine mode for structures.
+// If undefined, the default is GET_MODE_SIZE(DImode).
+#define MAX_FIXED_MODE_SIZE GET_MODE_SIZE(Pmode)
+
+// Make strings word-aligned so strcpy from constants will be faster.
+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
+ ((TREE_CODE (EXP) == STRING_CST \
+ && (ALIGN) < FASTEST_ALIGNMENT) \
+ ? FASTEST_ALIGNMENT : (ALIGN))
+
+// Make arrays of chars word-aligned for the same reasons.
+#define DATA_ALIGNMENT(TYPE, ALIGN) \
+ (TREE_CODE (TYPE) == ARRAY_TYPE \
+ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
+ && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
+
+// Set this nonzero if move instructions
+// will actually fail to work
+// when given unaligned data.
+#define STRICT_ALIGNMENT 1
+
+// Generating Code for Profiling.
+#define FUNCTION_PROFILER(FILE,LABELNO) (abort (), 0)
+
+// Trampolines for Nested Functions.
+#define TRAMPOLINE_SIZE (4)
+
+// Alignment required for trampolines, in bits.
+#define TRAMPOLINE_ALIGNMENT 32
+
+// An alias for the machine mode
+// used for memory references
+// to functions being called,
+// in `call' RTL expressions.
+#define FUNCTION_MODE QImode
+
+// The register number of the stack pointer
+// register, which must also be a fixed register
+// according to `FIXED_REGISTERS'.
+#define STACK_POINTER_REGNUM MYARCH_SP
+
+// The register number of the frame
+// pointer register, which is used
+// to access automatic variables
+// in the stack frame.
+#define FRAME_POINTER_REGNUM MYARCH_SP
+
+// The register number of the arg pointer register,
+// which is used to access the function's argument list.
+#define ARG_POINTER_REGNUM MYARCH_SP
+
+// Register which has been marked
+// as fixed in FIXED_REGISTERS
+// and which is used with instructions
+// that need a temporary register.
+// ### The need for this register
+// ### will be removed when I figure
+// ### how to allocate the least used
+// ### hard-register when an instruction
+// ### need a temporary register.
+#define MYARCH_RTMP MYARCH_R15
+
+/* A macro whose definition is
+the name of the class to which
+a valid base register must belong.
+A base register is one used in
+an address which is the register
+value plus a displacement. */
+#define BASE_REG_CLASS GENERAL_REGS
+
+#define INDEX_REG_CLASS NO_REGS
+
+#define HARD_REGNO_OK_FOR_BASE_P(NUM) \
+ ((unsigned)(NUM) <= MYARCH_R15)
+
+// A C expression which is nonzero
+// if register number NUM is suitable
+// for use as a base register
+// in operand addresses.
+#ifdef REG_OK_STRICT
+#define REGNO_OK_FOR_BASE_P(NUM) \
+ (HARD_REGNO_OK_FOR_BASE_P(NUM) \
+ || HARD_REGNO_OK_FOR_BASE_P(reg_renumber[(NUM)]))
+#else
+#define REGNO_OK_FOR_BASE_P(NUM) \
+ ((NUM) >= FIRST_PSEUDO_REGISTER || HARD_REGNO_OK_FOR_BASE_P(NUM))
+#endif
+
+// A C expression which is nonzero
+// if register number NUM is suitable
+// for use as an index register
+// in operand addresses.
+#define REGNO_OK_FOR_INDEX_P(NUM) MYARCH_RTMP
+
+// The maximum number of bytes that
+// a single instruction can move
+// quickly between memory and registers
+// or between two memory locations.
+#define MOVE_MAX 4
+#define TRULY_NOOP_TRUNCATION(op,ip) 1
+
+// All load operations zero extend.
+#define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
+
+// A number, the maximum number of registers
+// that can appear in a valid memory address.
+#define MAX_REGS_PER_ADDRESS 1
+
+#define TRULY_NOOP_TRUNCATION(op,ip) 1
+
+// An alias for a machine mode name.
+// This is the machine mode that
+// elements of a jump-table should have.
+#define CASE_VECTOR_MODE Pmode
+
+// A C compound statement with a conditional `goto LABEL;'
+// executed if X (an RTX) is a legitimate memory address
+// on the target machine for a memory operand of mode MODE.
+#define GO_IF_LEGITIMATE_ADDRESS(MODE,X,LABEL) \
+ do { \
+ if (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) \
+ goto LABEL; \
+ if (GET_CODE (X) == SYMBOL_REF \
+ || GET_CODE (X) == LABEL_REF \
+ || GET_CODE (X) == CONST) \
+ goto LABEL; \
+ } while (0)
+
+// Run-time Target Specification.
+#define TARGET_CPU_CPP_BUILTINS() \
+ { \
+ builtin_define_std ("myarch"); \
+ builtin_define_std ("MYARCH"); \
+ }
+
+#define HAS_LONG_UNCOND_BRANCH true
+
+#endif /* GCC_MYARCH_H */
diff --git a/gcc/config/myarch/myarch.md b/gcc/config/myarch/myarch.md
new file mode 100644
index 0000000..aa6f582
--- /dev/null
+++ b/gcc/config/myarch/myarch.md
@@ -0,0 +1,473 @@
+;; MYARCH Machine description.
+;; Copyright (C) 2009-2014 Free Software Foundation, Inc.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; -------------------------------------------------------------------------
+;; Specific constraints, predicates and attributes
+;; -------------------------------------------------------------------------
+
+(include "constraints.md")
+(include "predicates.md")
+
+; Most instructions are two bytes long.
+(define_attr "length" "" (const_int 2))
+
+;; -------------------------------------------------------------------------
+;; nop instruction
+;; -------------------------------------------------------------------------
+
+(define_insn "nop"
+ [(const_int 0)]
+ ""
+ "inc8 %%0, 0")
+
+;; -------------------------------------------------------------------------
+;; Arithmetic instructions
+;; -------------------------------------------------------------------------
+
+(define_insn "addsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
+ (plus:SI
+ (match_operand:SI 1 "register_operand" "0,0,0,0")
+ (match_operand:SI 2 "myarch_general_operand" "r,Imm8,Im16,Im32")))]
+ ""
+ "@
+ add %0, %2
+ inc8 %0, %2
+ inc16 %0, %2
+ inc32 %0, %2"
+ [(set_attr "length" "2,2,4,6")])
+
+(define_insn "subsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
+ (minus:SI
+ (match_operand:SI 1 "register_operand" "0,0,0,0")
+ (match_operand:SI 2 "myarch_general_operand" "r,Imm8,Im16,Im32")))]
+ ""
+ "@
+ sub %0, %2
+ inc8 %0, -%2
+ inc16 %0, -%2
+ inc32 %0, -%2"
+ [(set_attr "length" "2,2,4,6")])
+
+(define_insn "mulsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (mult:SI
+ (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "mul %0, %2")
+
+(define_insn "divsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (div:SI
+ (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "div %0, %2")
+
+(define_insn "udivsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (udiv:SI
+ (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "divu %0, %2")
+
+(define_insn "modsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (mod:SI
+ (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "mod %0, %2")
+
+(define_insn "umodsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (umod:SI
+ (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "modu %0, %2")
+
+;; -------------------------------------------------------------------------
+;; Unary arithmetic instructions
+;; -------------------------------------------------------------------------
+
+(define_insn "one_cmplsi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (not:SI (match_operand:SI 1 "register_operand" "r")))]
+ ""
+ "not %0, %1")
+
+;; -------------------------------------------------------------------------
+;; Logical operators
+;; -------------------------------------------------------------------------
+
+(define_insn "andsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (and:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "and %0, %2")
+
+(define_insn "xorsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (xor:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "xor %0, %2")
+
+(define_insn "iorsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "or %0, %2")
+
+;; -------------------------------------------------------------------------
+;; Shifters
+;; -------------------------------------------------------------------------
+
+(define_insn "ashlsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ashift:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "sll %0, %2")
+
+(define_insn "ashrsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "sra %0, %2")
+
+(define_insn "lshrsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "srl %0, %2")
+
+;; -------------------------------------------------------------------------
+;; Move instructions
+;; -------------------------------------------------------------------------
+
+(define_expand "movqi"
+ [(set (match_operand:QI 0 "general_operand" "")
+ (match_operand:QI 1 "general_operand" ""))]
+ ""
+ {
+ if (!(reload_in_progress || reload_completed)) {
+ ;// If this is a store, force the value into a register.
+ if (MEM_P (operands[0])) operands[1] = force_reg (QImode, operands[1]);
+ }
+ })
+
+(define_insn "*movqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,W,r")
+ (match_operand:QI 1 "myarch_general_operand" "O,r,Imm8,r,W"))]
+ ""
+ "@
+ xor %0, %0
+ cpy %0, %1
+ li8 %0, %1
+ st8 %1, %0
+ ld8 %0, %1"
+ [(set_attr "length" "2,2,2,2,2")])
+
+(define_expand "movhi"
+ [(set (match_operand:HI 0 "general_operand" "")
+ (match_operand:HI 1 "general_operand" ""))]
+ ""
+ {
+ if (!(reload_in_progress || reload_completed)) {
+ ;// If this is a store, force the value into a register.
+ if (MEM_P (operands[0])) operands[1] = force_reg (HImode, operands[1]);
+ }
+ })
+
+(define_insn "*movhi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,W,r")
+ (match_operand:HI 1 "myarch_general_operand" "O,r,Imm8,Im16,r,W"))]
+ ""
+ "@
+ xor %0, %0
+ cpy %0, %1
+ li8 %0, %1
+ li16 %0, %1
+ st16 %1, %0
+ ld16 %0, %1"
+ [(set_attr "length" "2,2,2,4,2,2")])
+
+(define_expand "movsi"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (match_operand:SI 1 "general_operand" ""))]
+ ""
+ {
+ if (!(reload_in_progress || reload_completed)) {
+ ;// If this is a store, force the value into a register.
+ if (MEM_P (operands[0])) {
+ operands[1] = force_reg (SImode, operands[1]);
+ if (MEM_P (XEXP (operands[0], 0)))
+ operands[0] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[0], 0)));
+ } else if (MEM_P (operands[1]) && MEM_P (XEXP (operands[1], 0)))
+ operands[1] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[1], 0)));
+ }
+ })
+
+(define_insn "*movsi"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,W,r")
+ (match_operand:SI 1 "myarch_general_operand" "O,r,Imm8,Im16,Im32,r,W"))]
+ ""
+ "@
+ xor %0, %0
+ cpy %0, %1
+ li8 %0, %1
+ li16 %0, %1
+ li32 %0, %1
+ st32 %1, %0
+ ld32 %0, %1"
+ [(set_attr "length" "2,2,2,4,6,2,2")])
+
+(define_insn "*movsi"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (label_ref (match_operand 1 "" "")))]
+ ""
+ {
+ if (get_attr_length (insn) == 4)
+ return "gip %0\n\tinc8 %0, %%l1+2";
+ else if (get_attr_length (insn) == 6)
+ return "gip %0\n\tinc16 %0, %%l1+4";
+ else return "gip %0\n\tinc32 %0, %%l1+6";
+ }
+ [(set (attr "length")
+ (cond [(leu (abs (minus (match_dup 1) (pc))) (const_int 125)) (const_int 4)
+ (leu (abs (minus (match_dup 1) (pc))) (const_int 32763)) (const_int 6)] (const_int 8)))])
+
+(define_insn "*movsi"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operand:SI 1 "myarch_symbol_ref_operand" "S"))]
+ ""
+ "gip %0\n\tinc32 %0, %1+6"
+ [(set_attr "length" "8")])
+
+;; -------------------------------------------------------------------------
+;; Bit extend instructions
+;; -------------------------------------------------------------------------
+
+(define_insn "*zero_extendqisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
+ ""
+ "zxt %0, 8")
+
+(define_insn "*zero_extendhisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
+ ""
+ "zxt %0, 16")
+
+(define_insn "*sign_extendqisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
+ ""
+ "sxt %0, 8")
+
+(define_insn "*sign_extendhisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
+ ""
+ "sxt %0, 16")
+
+;; -------------------------------------------------------------------------
+;; Conditional set instructions
+;; -------------------------------------------------------------------------
+
+(define_code_iterator COND [ne eq lt le ltu leu gt ge gtu geu])
+(define_code_attr CC [(ne "ne") (eq "eq")
+ (lt "lt") (le "lte") (ltu "ltu") (leu "lteu")
+ (gt "gt") (ge "gte") (gtu "gtu") (geu "gteu")])
+
+(define_insn "*setif<CC>"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (COND:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "s<CC> %0, %2")
+
+;; -------------------------------------------------------------------------
+;; Conditional jump instructions
+;; -------------------------------------------------------------------------
+
+(define_insn "cbranchsi4"
+ [(set (pc)
+ (if_then_else (match_operator 0 "myarch_cmp_op"
+ [(match_operand:SI 1 "register_operand" "+r")
+ (match_operand:SI 2 "register_operand" "r")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+ {
+ char* s;
+
+ if (GET_CODE (operands[0]) == NE) s = "sne %1, %2\n\t";
+ else if (GET_CODE (operands[0]) == EQ) s = "seq %1, %2\n\t";
+ else if (GET_CODE (operands[0]) == LT) s = "slt %1, %2\n\t";
+ else if (GET_CODE (operands[0]) == LE) s = "slte %1, %2\n\t";
+ else if (GET_CODE (operands[0]) == LTU) s = "sltu %1, %2\n\t";
+ else if (GET_CODE (operands[0]) == LEU) s = "slteu %1, %2\n\t";
+ else if (GET_CODE (operands[0]) == GT) s = "sgt %1, %2\n\t";
+ else if (GET_CODE (operands[0]) == GE) s = "sgte %1, %2\n\t";
+ else if (GET_CODE (operands[0]) == GTU) s = "sgtu %1, %2\n\t";
+ else if (GET_CODE (operands[0]) == GEU) s = "sgteu %1, %2\n\t";
+ else abort();
+
+ static char str[200];
+
+ if (get_attr_length (insn) == 8)
+ sprintf (str, "%sgip %%%%%u\n\tinc8 %%%%%u, %%l3+4\n\tjnz %%1, %%%%%u",
+ s, MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP);
+ else if (get_attr_length (insn) == 10)
+ sprintf (str, "%sgip %%%%%u\n\tinc16 %%%%%u, %%l3+6\n\tjnz %%1, %%%%%u",
+ s, MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP);
+ else sprintf (str, "%sgip %%%%%u\n\tinc32 %%%%%u, %%l3+8\n\tjnz %%1, %%%%%u",
+ s, MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP);
+
+ return str;
+ }
+ [(set (attr "length")
+ (cond [(leu (abs (minus (match_dup 3) (pc))) (const_int 123)) (const_int 8)
+ (leu (abs (minus (match_dup 3) (pc))) (const_int 32761)) (const_int 10)] (const_int 12)))])
+
+;; -------------------------------------------------------------------------
+;; Unconditional jump instructions
+;; -------------------------------------------------------------------------
+
+(define_expand "call"
+ [(call (match_operand:QI 0 "memory_operand" "")
+ (match_operand 1 "general_operand" ""))]
+ "")
+
+(define_insn "*call"
+ [(call (mem:QI (match_operand:SI 0 "myarch_symbol_ref_operand" "S"))
+ (match_operand 1 "" ""))]
+ ""
+ {
+ static char str[200];
+
+ sprintf (str, "gip %%%%%u\n\tinc8 %%%%%u, 14\n\tinc8 %%%%0, -4\n\tst32 %%%%%u, %%%%0\n\tinc32 %%%%%u, %%0\n\tj %%%%%u, %%%%%u",
+ MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP);
+
+ return str;
+ }
+ [(set_attr "length" "10")])
+
+(define_insn "*call"
+ [(call (mem:QI (match_operand:SI 0 "register_operand" "r"))
+ (match_operand 1 "" ""))]
+ ""
+ {
+ static char str[200];
+
+ sprintf (str, "gip %%%%%u\n\tinc8 %%%%%u, 8\n\tinc8 %%%%0, -4\n\tst32 %%%%%u, %%%%0\n\tj %%%%%u, %%0",
+ MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP);
+
+ return str;
+ }
+ [(set_attr "length" "10")])
+
+(define_expand "call_value"
+ [(set (match_operand 0 "" "")
+ (call (match_operand:QI 1 "memory_operand" "")
+ (match_operand 2 "" "")))]
+ "")
+
+(define_insn "*call_value_indirect"
+ [(set (match_operand 0 "register_operand" "=r")
+ (call (mem:QI (match_operand:SI 1 "register_operand" "r"))
+ (match_operand 2 "" "")))]
+ ""
+ {
+ static char str[200];
+
+ sprintf (str, "gip %%%%%u\n\tinc8 %%%%%u, 8\n\tinc8 %%%%0, -4\n\tst32 %%%%%u, %%%%0\n\tj %%%%%u, %%1",
+ MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP);
+
+ return str;
+ }
+ [(set_attr "length" "10")])
+
+(define_insn "indirect_jump"
+ [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
+ ""
+ "j %15, %0")
+
+(define_insn "jump"
+ [(set (pc) (label_ref (match_operand 0 "" "")))]
+ ""
+ {
+ static char str[200];
+
+ if (get_attr_length (insn) == 6)
+ sprintf (str, "gip %%%%%u\n\tinc8 %%%%%u, %%l0+4\n\tj %%%%%u, %%%%%u",
+ MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP);
+ else if (get_attr_length (insn) == 8)
+ sprintf (str, "gip %%%%%u\n\tinc16 %%%%%u, %%l0+6\n\tj %%%%%u, %%%%%u",
+ MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP);
+ else sprintf (str, "gip %%%%%u\n\tinc32 %%%%%u, %%l0+8\n\tj %%%%%u, %%%%%u",
+ MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP);
+
+ return str;
+ }
+ [(set (attr "length")
+ (cond [(leu (abs (minus (match_dup 0) (pc))) (const_int 123)) (const_int 6)
+ (leu (abs (minus (match_dup 0) (pc))) (const_int 32761)) (const_int 8)] (const_int 10)))])
+
+;; -------------------------------------------------------------------------
+;; Prologue & Epilogue
+;; -------------------------------------------------------------------------
+
+(define_expand "prologue"
+ [(const_int 0)]
+ ""
+ {
+ myarch_expand_prologue ();
+ DONE;
+ })
+
+(define_expand "epilogue"
+ [(return)]
+ ""
+ {
+ myarch_expand_epilogue ();
+ DONE;
+ })
+
+(define_insn "returner"
+ [(return)]
+ "reload_completed"
+ {
+ static char str[200];
+
+ sprintf (str, "ld32 %%%%%u, %%%%0\n\tinc8 %%%%0, 4\n\tj %%%%%u, %%%%%u",
+ MYARCH_RTMP, MYARCH_RTMP, MYARCH_RTMP);
+
+ return str;
+ }
+ [(set_attr "length" "6")])
diff --git a/gcc/config/myarch/myarch.opt b/gcc/config/myarch/myarch.opt
new file mode 100644
index 0000000..7b0ebdd
--- /dev/null
+++ b/gcc/config/myarch/myarch.opt
@@ -0,0 +1,21 @@
+; MYARCH compiler port options.
+
+; Copyright (C) 2015 Free Software Foundation, Inc.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 3, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+; for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING3. If not see
+; <http://www.gnu.org/licenses/>.
+
+; Ignored by the compiler
+mno-crt0
+Target RejectNegative
diff --git a/gcc/config/myarch/predicates.md b/gcc/config/myarch/predicates.md
new file mode 100644
index 0000000..a2fc085
--- /dev/null
+++ b/gcc/config/myarch/predicates.md
@@ -0,0 +1,29 @@
+;; MYARCH predicate definitions.
+;; Copyright (C) 2015 Free Software Foundation, Inc.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; -------------------------------------------------------------------------
+;; Predicates
+;; -------------------------------------------------------------------------
+
+(define_predicate "myarch_general_operand"
+ (match_code "mem,const_int,reg,subreg,const"))
+
+(define_predicate "myarch_symbol_ref_operand"
+ (match_code "symbol_ref"))
+
+(define_predicate "myarch_cmp_op"
+ (match_code "ne,eq,lt,le,ltu,leu,gt,ge,gtu,geu"))
diff --git a/gcc/config/myarch/t-myarch b/gcc/config/myarch/t-myarch
new file mode 100644
index 0000000..dc92304
--- /dev/null
+++ b/gcc/config/myarch/t-myarch
@@ -0,0 +1,16 @@
+# MYARCH Target Makefile Fragment.
+# Copyright (C) 2015 Free Software Foundation, Inc.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published
+# by the Free Software Foundation; either version 3, or (at your
+# option) any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
diff --git a/libgcc/config.host b/libgcc/config.host
index 4b15895..15e89cd 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -156,6 +156,9 @@ mips*-*-*)
fi
tmake_file="${tmake_file} t-softfp"
;;
+myarch-*-*)
+ cpu_type=myarch
+ ;;
nds32*-*)
cpu_type=nds32
;;
@@ -918,6 +921,10 @@ moxie-*-rtems*)
msp430*-*-elf)
tmake_file="$tm_file t-crtstuff t-fdpbit msp430/t-msp430"
;;
+myarch-*-elf)
+ tmake_file="myarch/t-myarch t-softfp-sfdf t-softfp-excl t-softfp"
+ extra_parts="$extra_parts crti.o crtn.o crtbegin.o crtend.o"
+ ;;
nds32*-elf*)
# Basic makefile fragment and extra_parts for crt stuff.
# We also append c-isr library implementation.
diff --git a/libgcc/config/myarch/crti.S b/libgcc/config/myarch/crti.S
new file mode 100644
index 0000000..134fb4e
--- /dev/null
+++ b/libgcc/config/myarch/crti.S
@@ -0,0 +1,40 @@
+# MYARCH crti.S
+#
+# Copyright (C) 2009-2014 Free Software Foundation, Inc.
+#
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 3, or (at your option) any
+# later version.
+#
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# Under Section 7 of GPL version 3, you are granted additional
+# permissions described in the GCC Runtime Library Exception, version
+# 3.1, as published by the Free Software Foundation.
+#
+# You should have received a copy of the GNU General Public License and
+# a copy of the GCC Runtime Library Exception along with this program;
+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+# <http://www.gnu.org/licenses/>.
+
+# This file just make a stack frame for the contents of the .fini and
+# .init sections. Users may put any desired instructions in those
+# sections.
+
+ .file "crti.S"
+
+ .section ".init"
+ .global _init
+ .type _init, @function
+ .p2align 1
+_init:
+
+ .section ".fini"
+ .global _fini
+ .type _fini,@function
+ .p2align 1
+_fini:
diff --git a/libgcc/config/myarch/crtn.S b/libgcc/config/myarch/crtn.S
new file mode 100644
index 0000000..5a438a2
--- /dev/null
+++ b/libgcc/config/myarch/crtn.S
@@ -0,0 +1,38 @@
+# MYARCH crtn.S
+#
+# Copyright (C) 2009-2014 Free Software Foundation, Inc.
+#
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 3, or (at your option) any
+# later version.
+#
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# Under Section 7 of GPL version 3, you are granted additional
+# permissions described in the GCC Runtime Library Exception, version
+# 3.1, as published by the Free Software Foundation.
+#
+# You should have received a copy of the GNU General Public License and
+# a copy of the GCC Runtime Library Exception along with this program;
+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+# <http://www.gnu.org/licenses/>.
+
+# This file just makes sure that the .fini and .init sections do in
+# fact return. Users may put any desired instructions in those sections.
+# This file is the last thing linked into any executable.
+
+ .file "crtn.S"
+
+ .section ".init"
+ ld32 %1, %0
+ inc8 %0, 4
+ j %1, %1
+
+ .section ".fini"
+ ld32 %1, %0
+ inc8 %0, 4
+ j %1, %1
diff --git a/libgcc/config/myarch/sfp-machine.h b/libgcc/config/myarch/sfp-machine.h
new file mode 100644
index 0000000..080e323
--- /dev/null
+++ b/libgcc/config/myarch/sfp-machine.h
@@ -0,0 +1,61 @@
+#define _FP_W_TYPE_SIZE 32
+#define _FP_W_TYPE unsigned long
+#define _FP_WS_TYPE signed long
+#define _FP_I_TYPE long
+
+/* The type of the result of a floating point comparison. This must
+ match `__libgcc_cmp_return__' in GCC for the target. */
+typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
+#define CMPtype __gcc_CMPtype
+
+#define _FP_MUL_MEAT_S(R,X,Y) \
+ _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_D(R,X,Y) \
+ _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_Q(R,X,Y) \
+ _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_loop(S,R,X,Y)
+#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
+#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
+#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
+#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
+#define _FP_NANSIGN_S 0
+#define _FP_NANSIGN_D 0
+#define _FP_NANSIGN_Q 0
+
+#define _FP_KEEPNANFRACP 1
+#define _FP_QNANNEGATEDP 0
+
+/* Someone please check this. */
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
+ do { \
+ if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \
+ && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \
+ { \
+ R##_s = Y##_s; \
+ _FP_FRAC_COPY_##wc(R,Y); \
+ } \
+ else \
+ { \
+ R##_s = X##_s; \
+ _FP_FRAC_COPY_##wc(R,X); \
+ } \
+ R##_c = FP_CLS_NAN; \
+ } while (0)
+
+/* Not checked. */
+#define _FP_TININESS_AFTER_ROUNDING 0
+
+#define __LITTLE_ENDIAN 1234
+#define __BIG_ENDIAN 4321
+
+# define __BYTE_ORDER __LITTLE_ENDIAN
+
+/* Define ALIASNAME as a strong alias for NAME. */
+# define strong_alias(name, aliasname) _strong_alias(name, aliasname)
+# define _strong_alias(name, aliasname) \
+ extern __typeof (name) aliasname __attribute__ ((alias (#name)));
+
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