mtlo/mflo instructions when issue width is increased (MIPS 5kc)

[Cherry Vanc]

I added a functional unit to the MIPS 5kc backend for memory
operations and noticed that a function started getting mtlo / mflo
instructions in the prologue/epilogue. The function does not have any
mult/div instructions.

When I debug the source of these instructions, I can only tap into the
code path when GCC is looking for the instruction suiting the RTL
pattern (final.c).

Why are these instructions being generated when I simply just added a
functional unit to the pipeline description ? How can I debug why they
are being generated in the first place ?

Thanks