Problem while writing Machine-description.

[Georg-Johann Lay]

Peter Kuschnerus schrieb:
> Hi,
> 
> I have instructions with variants to yield the result in register,
> promoted to either signdness (unsigned or signed).
> I aim to use the variant with signed promotion, if the type is signed,
> and otherwise to use the variant with unsigned ptomotion.
> 
> I try this as follows:
> 
> The macro PROMOTE_MODE is defined that way,
> that all modes are promoted to full size of registers (DImode),
> with the same signedness as the type.
> 
> The define_insn trys to get the promoted signdness of the output value
> by using the macro SUBREG_PROMOTED_UNSIGNED_P,
> to check which variant of instruction to be used.
> 
> The define_insn look this:
> 
> (define_insn "addsi3"
>   [(set (subreg:SI (match_operand:SI 0 "register_operand" "=r") 0)
>         (plus:SI (match_operand:SI 1 "register_operand" "%r")
>                  (match_operand:SI 2 "register_operand" "r")))]
>   ""
> {
>   if (SUBREG_PROMOTED_UNSIGNED_P(operands[0]))
>     return "add (unsigned32)%0, %1, %2";
>   return "add (signed32)%0, %1, %2";
> })

This pattern makes no sense to me.

SI-subreg of SI is trivial and can be removed.  operand0 is a 
register_operand.  It might be a subreg for other reasons, but then you 
run into problems because nested subregs are not allowed.

In struct RTL there are no subregs at all, this in the insn template you 
will never see a subreg (or your compiler is completely broken).

>>From the macro I get allways FALSE.
> I tried varying the RTL-expression,
> but I did not get any other than FALSE from SUBREG_PROMOTED_UNSIGNED_P.
> 
> I wonder what I am doing wrong.
> I do not know if this way is possible at all.
> Please does someone know a solution.

Try zero_extend or sign_extend patterns that also allow memory operands.

Alternatively, allow these operands in your mov predicate.  Reload knows 
how to handle 1-operand rtxes: It will reload the inner operand, not the 
operand as a whole.


Johann