L2 cache not optimally set for PowerPC 8548 (e500v2 core family) ?

[yon ar c'hall]

Hi all,

Before gcc-4.7.0, the PowerPC cpu type "8548" was set as a dummy
entry, pointing to "8540" settings. Thus, it was bound to the
ppc8540_cost structure, in which L2 cache is set to 256 (see
gcc/config/rs6000/rs6000.c).

Freescale MPC8548E PowerQUICC III processors are based on e500v2
cores, whose L2 cache size is 512 KB.

Would it mean the PowerPC "8548" (e500v2 family core) target is not
optimally processed in gcc, at least regarding the L2 cache ? (the
"8548" cpu type has even been fired, starting from gcc-4.7.x series).

Thanks,
Yon