Exception/instruction barrier

Hendrik Greving hendrik.greving.intel@gmail.com
Fri Aug 30 18:00:00 GMT 2013

Following problem: Below, the instruction
my_insn_can_jump_to_coolLabel is an instruction that can raise a
fault, that is subsequently handled by a higher OS like code, that
then will always jump to B3. I believe similar stuff exists in the
Linux kernel. What happens is that some code from B3 gets hoisted to
B1' (some base address from a complex address in B3, I suspect CSE).
The base address is then missing in case we 'jump' to B3 if an
exception had been raised.

asm volatile("my_insn_can_semantically_jump_to_B3 %0, %1", "=r, r")
         |    \
         |     \
         |        B2
         |      /
         |    /

First I thought that I might be able to make a jump_insn out of
my_insn somehow. But I think GCC doesn't support jump_insn with a
target register other than PC at the same time?

Is there anything like instruction barriers I can somehow support at
codeLabel maybe? How does the Linux kernel do this (if so)?

Hendrik Greving

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