Unable to remove pipeline stalls

[Deepti Sharma]

Hello All,

I am facing one issue with pipeline stalls. My compiler generates below
assembly:
 MOVE AR2, _rec2
 MOVE AR0, _rec1
 MOVE R3, (AR2)+  //Writes to R3
 MOVE (AR0)+, R3  //Reads from R3; Stall Created
 MOV  AR1, AR0
 MOV  AR0, AR2
 MOVE R2, (AR0)+  // 
 MOVE (AR1)+, R2  // stall
 MOVE R1, (AR0)+  // 
 MOVE (AR1)+, R1  // stall
 MOVE R0, (AR0,0) 
 MOVE (AR1,0), R0  //stall

Below is my test case:

---snip test.c ---
typedef struct MyRec
{
int a;
int b;
int c;
int d;
} sObj;

sObj *r1, *r2;

void main(void)
{
*r1 = *r2;
}
---/snip test.c ---

The command line option I am using is:
./cc1 -O2 -fschedule-insns -frename-registers test.c

Why the instruction scheduling is not able to reschedule instructions to
prevent the stall? The instructions have a latency '1'. 
I have the pipeline descriptions for it defined:

(define_attr "ATTR1" "none, mem1, mem2, mem3"
 (const_string "none"))

(define_attr "ATTR2" "none, op1, op2"
 (const_string "none"))

(define_cpu_unit "UNIT1, UNIT2, UNIT3, UNIT4")

(define_insn_reservation "mem" 1 (and (eq_attr "ATTR1" "mem1") (eq_attr
"ATTR2" "none"))  "UNIT1|UNIT2")
....
....
 (define_insn "*movsi"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=z,z,x,x, xz,co1 ")
        (match_operand:SI 1 "general_operand"      " z,x,z,x, co1,xz "))]
  ""
  "@
  MOV %0, %1
  MOVE %0, %1
  MOVE %0, %1
  MOVE %0, %1
  MOVE %0, %1
  MOVE %0, %1"
  [(set_attr "ATTR1" "mem1, mem1, mem1, mem1, mem1, mem1")
   (set_attr "ATTR2" "none, op1, op1, op1, op2, op1")])

For my case, I see that the movsi patterns 5th and 6th are getting matched.
The output of the sched1 pass comes as below:


;;   ======================================================
;;   -- basic block 2 from 7 to 20 -- before reload
;;   ======================================================

;;	  0-->     7 r62=`r1'                          
;;	  1-->     8 r63=`r2'                          :UNIT3
;;	  2-->    11 [r62++]=[r63++]                   :UNIT1|UNIT2
;;	  3-->    12 r65=r62                           :UNIT4
;;	  4-->    13 r64=r63                           :UNIT4
;;	  5-->    14 [r65++]=[r64++]                   :UNIT1|UNIT2
;;	  6-->    17 [r65++]=[r64++]                   :UNIT1|UNIT2
;;	  7-->    20 [r65]=[r64]                       :UNIT1|UNIT2

Any pointers for this issue will be helpful.

Thanks,
Deepti