Preventing scheduling of normal operations across calls to built-ins

[Ayonam Ray]

On 21 February 2012 18:51, Ian Lance Taylor <iant@google.com> wrote:
> Ayonam Ray <ayonam@gmail.com> writes:
>
>> I tried with inserting a set of a hard register in the RTL for the
>> built-in and a use of the same register in the addsi RTL.
>>
>> What I find is that the initial expression list itself gets reordered.
>>  For the test case above, I see an expression list like below:
>>
>>   __builtin_mvc_to_ccr (0, 8);
>>   __builtin_mvc_to_ccr (-1, 8);
>>   val1_7 = __builtin_mvc_from_ccr (8);
>>   __builtin_mvc_to_ccr (0, 8);
>>   val_4 = intVal_2(D) + intVal_2(D);
>>   val_6 = val_4 + oneVal1_5(D);
>>   val_8 = val_6 - oneVal_3(D);
>>   val_10 = val_8 + val1_7;
>>
>> As can be seen all the calls to the builtins have come together at the
>> top while the arithmetic operations are below them.  Any pointers to
>> solve this would be helpful.
>
> Please reply to the mailing list, not just to me.  Thanks.
>
> I don't see how this would be possible if the RTL is both setting and
> using the register.  So I think you need to show us the RTL.
>
> Ian

Sorry, I didn't mean to.  Didn't realize I was not replying to all.

Here's the RTL:

(define_insn "mvc_from_ccr"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "Y")]
                            UNSPEC_MVC_FROM_CCR))
   (set (reg:SI 0) (const_int 0))]
  ""
  "s2.mvc\t%1, %0"
  [(set_attr "length" "4")])


(define_insn "mvc_to_ccr"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "=Y")
                        (match_operand:SI 1 "register_operand" "r")]
                       UNSPEC_MVC_TO_CCR)
   (set (reg:SI 0) (const_int 0))]
  ""
  "s2.mvc\t%1, %0\;s1.nop"
  [(set_attr "length" "4")])

(define_expand "addsi3"
 [(parallel [(set (match_operand:SI 0 "register_operand" "")
                  (plus:SI (match_operand:SI 1 "nonmemory_operand" "")
                           (match_operand:SI 2 "nonmemory_operand" "")))
             (use (reg:SI 0))])]
  ""
  {
    if (GET_CODE(operands[1]) != REG  &&
        (   GET_CODE(operands[1]) != CONST_INT
         || ! satisfies_constraint_J(operands[1])))
      operands[1] = force_reg(SImode, operands[1]);

    if (GET_CODE(operands[2]) != REG  &&
        (   GET_CODE(operands[2]) != CONST_INT
         || ! satisfies_constraint_J(operands[2])))
      operands[2] = force_reg(SImode, operands[2]);
  })

(define_insn "*addsi3"
 [(set (match_operand:SI 0 "register_operand" "=r,r")
       (plus:SI (match_operand:SI 1 "register_or_const_int_operand" "%r,r")
                (match_operand:SI 2 "register_or_const_int_operand"  "r,J")))
  (use (reg:SI 0))]
  ""
  "@
   add\t%1, %2, %0
   addi\t%1, %2, %0"
  [(set_attr "length" "4")])


(define_insn "subsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
        (minus:SI (match_operand:SI 1 "nonmemory_operand" "r,r,J")
                  (match_operand:SI 2 "nonmemory_operand" "r,J,r")))
   (use (reg:SI 0))]
  ""
  "@
    sub\t%1, %2, %0
    subi\t%1, %2, %0
    sub\tr0, %2, %0\;addi\t%0, %1, %0"
  [(set_attr "length" "4,8,8")
] )


Thanks and regards
Ayonam