Unable to remove stall at shed2

[shweta_guptasairam]

I am compiling my test case with my compiler (gcc 4.2.4) for a 16 bit
processor, with the below command:
./cc1.exe  -O2 -frename-registers -fschedule-insns  -fdump-rtl-all
/cygdrive/d/test.c 
In the assembly of main stalls are getting generated :
	mov r3, (ar6,-52) //write to r3
	mov (ar0)+, r3 //use r3
	mov r2, (ar6,-48)
	mov (ar0)+, r2
	mov r1, (ar6,-44)
	mov (ar0)+, r1

In my md file I have defined pipeline description indicating stall between
two instructions.	
On analyzing the output of sched1 found that there are no stalls gets
generated

 	40 r73=[ar6-0x34]                   
	36 [r70++]=r71                     
	 43 r74=[ar6-0x30]                    
	 39 [r70++]=r72                       
	 50  r75=[ar6-0x2c]                    
	42 [r70++]=r73                       
	
 

In the output of .lreg file  instruction 205 is hown which is not present in
shed1 output

(insn 205 39 42 2 (set (reg:SI 73 [ gameobjs+8 ])
        (mem/s:SI (plus:SI (reg/f:SI 22 ar6)
                (const_int -52 [0xffffffcc])) [4 gameobjs+8 S4 A32])) (nil)
    (expr_list:REG_EQUIV (mem/s:SI (plus:SI (reg/f:SI 22 ar6)
                (const_int -52 [0xffffffcc])) [4 gameobjs+8 S4 A32])
        (nil)))

(insn 42 205 204 2 (set (mem:SI (post_inc:SI (reg/f:SI 70)) [0 S4 A32])
        (reg:SI 73 [ gameobjs+8 ])) (nil)
    (expr_list:REG_DEAD (reg:SI 73 [ gameobjs+8 ])
        (expr_list:REG_INC (reg/f:SI 70)
            (nil))))

I suspect that this instruction 205 is getting generated due to spilling but
I am not sure
This stall is not getting removed in sched2 also  
r0=[ar6-0x34]                     
[ar0++]=r0                        
 ar2=[ar6-0x30]                    
[ar0++]=ar2                       
 ar1=[ar6-0x2c]                    
 [ar0++]=ar1                       

Please guide how to remove stall in this case 

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