"rep ret" even for Intel CPUs?

[Ian Lance Taylor]

kevin diggs <diggskevin38@gmail.com> writes:

> Uh ... "rep; ret"? Where do I look to see what this is?

Some AMD processors have a one cycle pipeline stall when a "ret"
instruction is the target of a conditional jump or is immediately
preceded by a conditional jump.  To avoid this, gcc generates "rep; ret"
in those cases intead.  Since the "rep" prefix means nothing with the
"ret" instruction, this effectively becomes a two byte "ret"
instruction, and that is sufficient to avoid the pipeline bubble.

Ian