GCC 4.4.1 issue

[Andrew Haley]

On 07/07/2010 11:10 AM, keshav yadav wrote:
> Thanks Andrew for your answer,
> 
> if we use gcc 4.2.0 then there is no problem. So will you pls let us
> know how to fix this.

I don't think you can.  You have to allow reload a few registers to
work with.

> arm-linux-gnueabi-gcc_4.2.0   test.c -O
> If we do not use optimisation flag '-O' this also result in same error.
> 
> Is there any way to fix this issue.

Use fewer registers.  Your asm uses 14 registers; the ARM only has 16,
and gcc needs a stack pointer, a frame pointer, and a scratch
register or two.  Your asm is totally unreasonable.

Andrew.


> On Wed, Jul 7, 2010 at 2:29 PM, Andrew Haley <aph@redhat.com> wrote:
>> On 07/07/2010 07:54 AM, keshav yadav wrote:
>>>
>>> We Build tool chain for ARM architecture(cortex A8) and when we build
>>> below code we face Build error.
>>>
>>>
>>>
>>> arm-none-linux-gnueabi-gcc  test.c
>>>
>>> test.c: In function 'main':
>>> test.c:13: error: can't find a register in class 'GENERAL_REGS' while
>>> reloading 'asm'
>>> test.c:13: error: 'asm' operand has impossible constraints
>>>
>>>
>>> test.c
>>> int main(void)
>>> {
>>>         unsigned int u32PosFrac;
>>>         int s32PosInt;
>>>         int s16CoeffOrg[100][100];
>>>         unsigned int u32In3[(1024>>2)+4];
>>>         unsigned int* pu8In4;  //pu8In4 = (UInt8*)u32In3;
>>>         unsigned char*  u8Out;
>>>         unsigned int u32Step;
>>>         unsigned int u32TgtWidth;
>>>         asm volatile (
>>>                 "\n\t"
>>>                                 :
>>>                                 : "r" (pu8In4), "r" (s32PosInt), "r"
>>> (s16CoeffOrg), "r" (u32PosFrac), "r" (u8Out), "r" (u32Step), "r"
>>> (u32TgtWidth)
>>>                                 : "r2", "r3", "r4", "r5", "r6", "r7", "r8"
>>>                                 );
>>>         return 1;
>>> }
>>>
>>>
>>>
>>> Will you please let me know the reason and fix for this.
>>
>> Surely you've run out of registers.
>>
>> Andrew.
>>
>>