Is 4 byte -1 invalid code on most/all architectures?

[David Daney]

On 12/08/2010 04:41 PM, Jay K wrote:
>
> Hi. This is off topic, but I know there is expertise here and I'm a little lazy.
>

Evidently true.  The ISA manuals for all the processors you are 
interested in are available to you.

>
> We have a system where we need to read the code/data
> a function pointer points to, and if it contains
> a particular marker, treat it differently.
>
>
> The marker we use is a pointer-sized -1.
> On some targets, we also first check the alignment of the function pointer.
> ie: on targets with fixed size 4 byte instructions, 8 byte pointers, where
> alignment is checked, if the pointer is only 4-byte aligned, we don't do
> the read and assume the pointer is to "regular code".
> e.g. ppc64, sparc64, hppa64, mips64 if I recall correctly, which
> all have 4 byte instructions and require 8 byte reads to be 8 byte aligned.
>
>
> My question is two part:
> We target a moderate list of processors:
> tier 1: sparc, x86, powerpc
> tier 2: alpha, mips
> possible future: ia64, hppa
>
>
> Is -1 invalid code on all these?

No. On MIPS I think 0xffffffff -> SD $31,-1($31)

It is not likely this instruction would occur, but it is legal.

David Daney