Constraint modifier for partially overlaping operands

[Andrew Hutchinson]

Yes.

But we need to lower after combine and before register allocation.
I'm still figuring out how to do that.

Lowering before combine - in particular causes a lot of code bloat. This 
loose all optimization of conditional jumps, shifts etc.
In our case, most lowering is delayed until after reload. This retains 
the RTL optimization but is suboptimal for allocation and lacks enough 
forward propagation.

For a similar reason, not splitting wide types often produces far better 
code.

One exception is DImode which by default is  lowered at expand -since 
there are no  DImode instructions defined.
This ends up with pretty dire code since the built in expansion cant use 
a "carry" based pattern and we again miss
the RTL optimization at the wider level. 

It would seem we need to have target dependent pass order to improve on 
this significantly.


Andy








Richard Henderson wrote:
> On 10/16/2009 11:04 PM, Ian Lance Taylor wrote:
>> Andrew Hutchinson<andrewhutchinson@cox.net>  writes:
>>
>>> I can use "=" modifier to make operands use same register and early
>>> clobber "&" to avoid overlaps.
>>>
>>> Is it possible to have or construct a contraint that permits partial
>>> overlap operands. (which neither = or&  would allow)
>>> The case would be  wide types taking multiple hard registers.
>>>
>>> eg Input r20..23 Output r22..25
>>
>> There is no such constraint today.  I suppose it would be possible to
>> define such a constraint if it seemed useful.
>
> I'd much prefer if the port decomposed its double word operations and 
> used the lower-subreg pass to decompose the double word registers.  At 
> which point the register allocator has all of the information it needs 
> to do the right thing.
>
>
> r~
>