instruction ordering

[marian]

I have a question regarding the powerpc-eabi-gcc compiler. 

We currently use a commercial compiler for a 405 processor in a Xilinx
vertex FPGA and will be moving to the 440 in future. We are consistently
getting poor results with the gcc compiler in terms of free processor
times. This indicates to us the gcc compiler is producing inefficient
code. In looking at the assembly output there are a number of
instruction reversals between the commercial compiler and gcc. 

My question has the assembly ordering for the 405 and 440 been
optimised?