ins instruction is not produced in the assembly code (mips32r2)

[David Daney]

fanqifei wrote:
> Is there anyone can help?
> I am curious about how the insv pattern can be used in the compiling process.
> Otherwise, I have to write inline assembly code.
> Thanks very much!
> 

You don't state which compiler version you are using.  I would suggest 
trying a GCC-4.5 snapshot.  I know that some work has been recently done 
to make better use of INS.

If GCC-4.5 doesn't help, you could file a GCC bug report about this 
missed optimization.

David Daney



> 2009/12/16 fanqifei <fanqifei@gmail.com>:
>> Hello,
>> I am tring to compile a small c file using gcc4.1.2.
>> The source code:
>> struct test_foo {
>> unsigned int a:18;
>> unsigned int b:2;
>> unsigned int c:12;
>> };
>>
>> struct test_foo x;
>> unsigned int foo()
>> {
>>     unsigned int a=x.b;
>>     x.b=2;
>>     return a;
>> }
>>
>> the command: mipsel-linux-gcc -mips32r2 -O2 -c -Wall foo.c -o foo.o
>>
>> The corresponding disassembly code:
>> foo.o:     file format elf32-tradlittlemips
>> Disassembly of section .text:
>> 00000000 <foo>:
>>    0:   3c1c0000    lui gp,0x0
>>    4:   279c0000    addiu   gp,gp,0
>>    8:   0399e021    addu    gp,gp,t9
>>    c:   8f850000    lw  a1,0(gp)
>>   10:   3c03fff3    lui v1,0xfff3
>>   14:   3463ffff    ori v1,v1,0xffff
>>   18:   8ca20000    lw  v0,0(a1)
>>   1c:   3c040008    lui a0,0x8
>>   20:   00431824    and v1,v0,v1
>>   24:   00641825    or  v1,v1,a0
>>   28:   7c420c80    ext v0,v0,0x12,0x2
>>   2c:   03e00008    jr  ra
>>   30:   aca30000    sw  v1,0(a1)
>> The statement x.b=2 can be simply translated to lb and ins instructions( ins
>> is in mips32r2).
>>
>> I wonder how ins instrution can be produced.
>> More specifically, how can gcc generates the insv pattern in RTL?
>> Is it related to the coding style -- using bit filed or logical
>> operations(shift, and ...)?
>> Thanks.
>> Qifei
>>
>>
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