ins instruction is not produced in the assembly code (mips32r2)

[fanqifei]

The instruction sequence generated by gcc can be simply rewritten by
three instructions.
Apparently gcc should find the expression storing to bit-field and use
pattern insv. But it didn't.

gcc:
 10:   3c03fff3    lui v1,0xfff3
 14:   3463ffff    ori v1,v1,0xffff
 18:   8ca20000    lw  v0,0(a1)
 1c:   3c040008    lui a0,0x8
 20:   00431824    and v1,v0,v1
 24:   00641825    or  v1,v1,a0

with ins:
lw v0,0(a1)
ori a0, $0, 2
ins v0,v0,19,18


2009/12/18 Ineiev <ineiev@gmail.com>:
> On 12/18/09, fanqifei <fanqifei@gmail.com> wrote:
>> Is there anyone can help?
>> I am curious about how the insv pattern can be used in the compiling
>> process.
>> Otherwise, I have to write inline assembly code.
>
> Out of curiosity --- why do you think your executable has to use this pattern?
>
> Regards,
> Ineiev
>

-- 
        Qifei Fan