Bug with PPC 32-bit inline assembler [4.1.1 and 4.3.2]

[Ian Lance Taylor]

Tom St Denis <tstdenis@ellipticsemi.com> writes:

> Andrew Haley wrote:
>> Tom St Denis wrote:
>>> #define SQRADDSC(i, j)            \
>>> asm(                              \
>>>   " mullw  %0,%3,%4        \n\t" \
>>>   " mulhwu %1,%3,%4        \n\t" \
>>>   " xor    %2,%2,%2        \n\t" \
>>> :"=r"(sc0), "=r"(sc1), "=r"(sc2): "r"(i),"r"(j) : "%cc");
>>>
>>> #endif
>>>     
>> This isn't a bug: look for "earlyclobber" in the documentation.
>>   
>
> Adding =&r worked, however ... (this is the part where I complain
> perhaps needlessly :-) )
>
> This doesn't make sense.  In the subsequent line "mulhwu ..." I
> specifically asked for %3,%4 which is i and j respectively.  Yet,
> without early clobber it gives me sc0.    To me that sounds like a
> bug.  Maybe it's not the way the inline asm is "meant" to be used, but
> to someone who reads the code it's not obvious that %3 no longer means
> i.  Semantically it's as if I used "%1,%0,%4" as the operands for the
> 2nd line.

%3 will always be translated to the same register.  Presumably when it
was translated to sc0 on the second line, it was also translated to
sc0 on the first line.

Without the earlyclobber designation, for all gcc knows you are just
using a single instruction, for which an input and an output may be in
the same register.

Ian