Is it possible that gcc reorders a series of read/write operations?

[me22]

On Wed, Sep 3, 2008 at 21:11, Pan ruochen <panruochen@gmail.com> wrote:
>
> Can volatile do this? I thought volatile just forced GCC to read the
> memory location each time rather than cahed the value in a register.
> And I am interested in the details how your MIPS CPU hardware
> reordered instructions.
>

>From the latest C++0x draft, section 1.9 [intro.execution]:

  The semantic descriptions in this International Standard define a
parameterized nondeterministic abstract
  machine. This International Standard places no requirement on the
structure of conforming implementations.
  In particular, they need not copy or emulate the structure of the
abstract machine. Rather, conforming
  implementations are required to emulate (only) the observable
behavior of the abstract machine as explained
  below.

  The observable behavior of the abstract machine is its sequence of
reads and writes to volatile data and
  calls to library I/O functions.

(That's not the whole story, and C or C++03 may have phrased it
differently, of course.)

HTH,
~ Scott