Optimizing gcc for power through instruction rescheduling
Sun Sep 28 18:45:00 GMT 2008
I am trying to optimize gcc by scheduling processor instructions aimed at
reducing power consumption. Though this technique primarily used for VLIW
architectures so far, here i want to use this technique to solve this
problem for x86-64 architecture. Power can be reduced by the product of
capacitance loading and transition activity. Since bus wires have large
capacitance loading, the reduction of transition activities of buses will be
very effective in reducing total power consumption.
I would like to know how to hgo about doing this.
Any kind of suggestion would be very beneficial for me.
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