Disabling cache for some data

[Claudio Scordino]

John Love-Jensen wrote:
> Hi Claudio,
> 
> What "cache" are you referring?  In register optimization as a "cache"?
> CPU's L1 cache?  RAM's L2 cache?  FSB L3 cache?

My goal is to have data actually transferred on the bus. So, I think it's just 
CPU's cache that I want to disable for my data.

> 
> Is the memory array cache declared as volatile in the code?

Does the volatile command ensure that data is not cached on cpu's cache ?

Thanks,

         Claudio