Extracting information from GCC register allocation

Nikolaos Kavvadias nkavv@physics.auth.gr
Tue Nov 14 15:14:00 GMT 2006

Hash: SHA1
Hi there

i have a few questions about register allocation in GCC (mainly for
RISC targets).

First of all, it is true that GCC takes a rather complex way around
things. It seems to me that there are at least four passes for
register allocation:
lreg, greg, and a couple of reload passes (postreload?, rnreg? i'm not
sure). This is understandable due to the incremental way that things have
progressed. Now, to be more specific:

1. Is it possible to emit something close to assembly with
pseudo-registers instead of registers? I mean, is it possible to do this
just before each one of these passes? Or would it be possible to
devise such pass (e.g. an emitter just prior greg). I can see some RTL
stuff with pseudos (e.g. *.lreg) but is it semantically complete in
order to be possible to translate it to assembly (even though with
infinite registers)?

2. Is it possible to explicitly mark the fill/spill instructions (or
RTL statements) in such RTL dumps?

3. Supposedly a <machine.h> description is devised that has a
ridiculously large of registers (so that spills *almost* never will
Will this approach the effect of register allocation for infinite
registers or there exist other GCC-specific constraints. What are the
limits in the number of registers, registers in classes, allocable
registers etc (i've seen some very bad restrictions in LCC due to the
use of masks with host-dependent size).

And a last one:

4. There is some discussion around gmp/mpfr support in GCC lately. Are
we close to using arbitrary-size integers throught the GCC

Kind regards
Nikolaos Kavvadias

Version: GnuPG v1.4.0 (MingW32)
Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org

More information about the Gcc-help mailing list