Makefile issue
Dima Sorkin
dima.sorkin@gmail.com
Tue Jul 18 14:05:00 GMT 2006
On 7/3/06, Parikshat Dubey wrote:
> c3.o:c3.c
> $(CC) -$INCLUDE -$(CFLAGS) -I. -I$(SRC) -c $<
>
> all:parikshit
> $(CC) -$(OBJS) -$INCLUDE -$(CFLAGS) -$LIBS --g -o parikshit
>
>
> As far as my knowledge goes '$< ' will automatically search the mentioned
> source file in the folder mentioned by SRC .for example in this case
> a1.o:a1.c
> $(CC) -$INCLUDE -$(CFLAGS) -I. -I$(SRC) -c $<
> '$<' will automatically search the source file in the path mentioned by
> SRC(/Module/src) macro.
> i.e.above thing will automatically search source file a1.c in /Module/src/
> Module1/a1.c
No. "-I" is tells the _gcc_compiler_ where to look for "include"-files.
The Make program does not account for this, it cannot know.
There are ways to supply search paths for _make_ , but you will
have to read a lot of documentation, writing makefiles is a mastery
of itself. You may read
aegis.sourceforge.net/auug97.pdf
http://make.paulandlesley.org/autodep.html
Dima.
P.S.
By the way, the lines of the form
" $(CC) -$INCLUDE -$(CFLAGS) -I. -I$(SRC) -c $<"
are redundant, make generates these calls by itself.
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