interrupt handling with GCC

sashti srinivasan
Sun Dec 19 10:03:00 GMT 2004

   I take the example of SPARC.  Each interrupt is
associated with a number and CPU jumps to a particular
address on interrupt depending on the number.  That
address handles the interrupt, i.e, ISR should be at
that number.  There will be space only for four
instructions.  In gcc tool-chain, how to write ISR? 
Is writing the OPCODES to the address corresponding to
the interrupt number the only way?  Any other smart
techniques exist?  Please guide me.


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