Special instructions in inline assembler

John Yates jyates@netezza.com
Mon Dec 15 20:59:00 GMT 2003


Derek,

I will be very surprised if someone comes forth with a way to do this
in GCC.  Apollo's DN10K architecture had such a feature.  Getting our
compiler to exploit it entailed significant work in multiple phases,
especially the register allocator.  From personal experience I can
tell you that register pairs and classic Chaitin register coloring
register allocators do not mesh particularly well.

/john

-----Original Message-----
From: Derek Roberts [mailto:derek@camroberts.org.uk]
Sent: Friday, December 12, 2003 1:06 PM
To: gcc-help@gcc.gnu.org
Subject: Special instructions in inline assembler


Hello,

I have a mips-like processor that I'm playing with that I've implemented a 
couple of 64-bit instructions in.
When I use the special instruction, I load or store two 32-bit registers 
from or to adjacent dwords in memory.  The catch is this:  the register 
named in the instruction must be even (i.e. r0, r2, r4 etc) and the second 
register that gets "clobbered" is related to the first by a fixed increment 
of one.

My question is this:
Is it possible to write this instruction in inline assembler ? I can't seem 
to find a constraint that works. Currently I'm using r2 and r3, declaring 
them as clobbered and doing a copy to the registers that C supplied. This 
is nearly as inefficient as doing the two dword loads.

If not, how much effort is required to support it in another way like 
porting the C compiler directly ?

Many thanks to anyone who can help,
Derek Roberts



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