Register Spilling

[Falk Hueffner]

Umar Janjua <Umar.Janjua@cl.cam.ac.uk> writes:

> Well, if that is the case, then , how advantageous would be
> considering cache locality for such register spilled values, so that
> instructions that require spilled values do not cause cache miss.

Most stack frames easily fit into L1, so probably not a lot. There has
been some work on this motivated by other things, though; see "Optimal
Stack Slot Assignment in GCC" by Naveen Sharma and Sanjiv Kumar Gupta
in the GCC summit proceedings
(http://www.linux.org.uk/~ajh/gcc/gccsummit-2003-proceedings.pdf)

-- 
	Falk