ELF instruction for section and branch.

Gagneet Singh gagneet@acmet.com
Fri Dec 26 04:41:00 GMT 2003


Hi!

> If you want help, you must provide a complete test case.  We 
> can not guess what you are doing.

Sorry about leaving out the test case examples...

Also, I did not know about the binutils mailing list and thought that
this list will be the one for the Assembler porting also.. my apologies
again..

Well! For now I am sending the example (sending the complete source for
both MIPS and Intel) to this list until my confirmation about the other
oe comes in...  This is just as a followup and closeure of this thread.

MIPS Assembly Output:
----------------------
;==========================================================
;Created on  :  18th December 2003

;Created by  :  Gagneet Singh

;Description : 
; This test file is to test the behaviour of the branch instruction with
; a label. The label is defined in a seperate code section. 
; I have as yet to succeed in creating a assembly output from a C file, 
; which simulates the condition given above. 
; Thus, the assembly file is being hand-coded.

;Test case History:
; Created for testing the result of 
; "a branch instruction is referencing a label defined in another
section".

;Phenomenon:
; For IEEE the file is being processed properly. This has been
; seen using the MIPS debugger. But, for ELF formats
; when tested using the GDB simulator created for ELF output, it
; is not.

;Hypothesis: 
; In the debugger if we view the 'Symbols' window we see that the 
; assembly file has been described with two sections - data and code.
; The data section is of size 4 bytes, while the code section comprises
; both the code sections and is of size 80 bytes.

;Expected behaviour:
; The label given at TestNode2 is referenced properly in IEEE format
when 
; the branch instruction at TestNode1 references it. The code flow goes
to
; the address referenced by the label L1 (TestNode1).
; The ELF behaviour is not known.

;Reference: Mails from the GCC Mailing List 
;===============================================================
	module section_branch_asm_c
n_data section data medium align=4,4
	align 4
	public _globalVar
_globalVar:
	align 4
	dw 10
f_code section code isa32 align=4,4
	align 4
	public _main
_main:
	addiu	sp, sp, -8
	sw	ra, 4(sp)
	sw	r16, 0(sp)
	ori	r13, r0, 0xa
	ori	r2, r0, 0x1
	beq	r2, r0, L1
	nop	
	addu	r16, r13, r0
	addu	r4, r13, r0
	jal	_fsiBranchLabel
	nop	

;TestNode2
L1:
	addu	r2, r16, r0
	j	L0
	nop	
L0:
	lw	ra, 4(sp)
	lw	r16, 0(sp)
	addiu	sp, sp, 8
	jr	ra
	nop

f_code section code isa32 align=4,4
	align 4
	public _fsiBranchLabel
_fsiBranchLabel:
	symbol_a "",9,0,4
	addu	r12, r4, r0
	slti	r2, r4, 10

;TestNode1
	bne	r2, r0, L1
	nop	
	addiu	r12, r4, 1
	sw	r4, sdaoff(_globalVar)(gp)
L4:
	addu	r2, r12, r0
	j	L3
	nop	
L3:
	jr	ra
	nop

	end

====================================================

GCC Intel i686 Assembly Language Output:
-------------------------------
#==========================================================
#Created on  :  18th December 2003

#Created by  :  Gagneet Singh

#Description : 
# This test file is to test the behaviour of the branch instruction with
# a label. The label is defined in a separate code section. 
# I have as yet to succeed in creating a assembly output from a C file, 
# which simulates the condition given above. 
# Thus, the assembly file is being hand-coded.

#Test case History:
# Created for testing the result of 
# "a branch instruction is referencing a label defined in another
section".

#Phenomenon:
# Only one section can be defined by the '.text', if I substitute
# the section name  as '.text1' if gives and error.

#Hypothesis: 
# Issues an error for TestNode3 saying "secbr.s:93: Error: Unknown
pseudo-op: 
# `.text1'".

#Expected behaviour:
# As yet to determine, otherwise the file should compile and link
properly.

#Reference:
#============================================================
	.file	1 "secbr.c"

 # -G value = 8, Cpu = 3000, ISA = 1
 # GNU C version 2.7 (mips-tx39-elf) compiled by GNU C version
2.7-97r1a.
 # options passed: 
 # options enabled:  -fpeephole -ffunction-cse -fkeep-static-consts
 # -freg-struct-return -fcommon -fverbose-asm -fgnu-linker -mgas
 # -msoft-float -meb -m3900 -mcpu=3000

gcc2_compiled.:
__gnu_compiled_c:
	.globl	globalVar
	.sdata
	.align	2
globalVar:
	.word	10

	.text
	.align	2
	.globl	main
	.ent	main
main:
	.frame	$fp,16,$31		# vars= 8, regs= 2/0, args= 0,
extra= 0
	.mask	0xc0000000,-4
	.fmask	0x00000000,0
	subu	$sp,$sp,16
	sw	$31,12($sp)
	sw	$fp,8($sp)
	move	$fp,$sp
	jal	__main
	li	$2,10			# 0x0000000a
	sw	$2,0($fp)
	lw	$2,0($fp)
	li	$3,10			# 0x0000000a
	bne	$2,$3,$L2
	lw	$2,0($fp)
	sw	$2,4($fp)
	addu	$2,$2,1
	sw	$2,0($fp)
	lw	$4,4($fp)
	jal	fsiBranchLabel
	sw	$2,0($fp)

#TestNode2
$L2:
	lw	$3,4($fp)
	move	$2,$3
	b	$L1
$L1:
	move	$sp,$fp			# sp not trusted here
	lw	$31,12($sp)
	lw	$fp,8($sp)
	addu	$sp,$sp,16
	j	$31
	.end	main

#TestNode3
	.text
	.align	2
	.globl	fsiBranchLabel
	.ent	fsiBranchLabel
fsiBranchLabel:
	.frame	$fp,16,$31		# vars= 8, regs= 1/0, args= 0,
extra= 0
	.mask	0x40000000,-8
	.fmask	0x00000000,0
	subu	$sp,$sp,16
	sw	$fp,8($sp)
	move	$fp,$sp
	sw	$4,0($fp)
	lw	$2,0($fp)
	slt	$3,$2,10
#TestNode1	
	bne	$3,$0,$L1
	lw	$2,0($fp)
	sw	$2,globalVar
	addu	$2,$2,1
	sw	$2,0($fp)
$L4:
	lw	$3,0($fp)
	move	$2,$3
	b	$L2
$L3:
	move	$sp,$fp			# sp not trusted here
	lw	$fp,8($sp)
	addu	$sp,$sp,16
	j	$31
	.end	fsiBranchLabel




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