[gcc r17-648] riscv: Fix SSP assembly with xtheadmemidx [PR 125320]

[Xi Ruoyao]

https://gcc.gnu.org/g:aac8c3738bb26b72281e55778428af559c9bb032

commit r17-648-gaac8c3738bb26b72281e55778428af559c9bb032
Author: Xi Ruoyao <xry111@xry111.site>
Date:   Fri May 15 11:46:35 2026 +0800

    riscv: Fix SSP assembly with xtheadmemidx [PR 125320]
    
    The m constraint accepts memory operands suitable for memory load/store
    instructions in extensions, not only the ld/sd instructions.  So we
    cannot always use ld/sd in the SSP instruction sequences.
    
    Call riscv_output_move() for the correct assembly template instead.
    
            PR target/125320
    
    gcc/
    
            * config/riscv/riscv.md (stack_protect_test_<mode>): Call
            riscv_output_move() instead of hard coding <load>.
            (stack_protect_set_<mode>): Call riscv_output_move() instead of
            hard coding <load> and <store>.
    
    gcc/testsuite/
    
            * gcc.target/riscv/pr125320.c: New test.

Diff:
---
 gcc/config/riscv/riscv.md                 | 22 ++++++++++++++++++++--
 gcc/testsuite/gcc.target/riscv/pr125320.c | 10 ++++++++++
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 4a5d90e0f6aa..8615a2ebad44 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -4526,7 +4526,16 @@
 	 UNSPEC_SSP_SET))
    (set (match_scratch:GPR 2 "=&r") (const_int 0))]
   ""
-  "<load>\t%2, %1\;<store>\t%2, %0\;li\t%2, 0"
+  {
+    rtx moves[][2] = {
+      {operands[2], operands[1]},
+      {operands[0], operands[2]},
+    };
+    for (rtx *op: moves)
+      output_asm_insn (riscv_output_move (op[0], op[1]), op);
+
+    return "li\t%2, 0";
+  }
   [(set_attr "type" "multi")
    (set_attr "length" "12")])
 
@@ -4566,7 +4575,16 @@
 	 UNSPEC_SSP_TEST))
    (clobber (match_scratch:GPR 3 "=&r"))]
   ""
-  "<load>\t%3, %1\;<load>\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0"
+  {
+    rtx moves[][2] = {
+      {operands[3], operands[1]},
+      {operands[0], operands[2]},
+    };
+    for (rtx *op: moves)
+      output_asm_insn (riscv_output_move (op[0], op[1]), op);
+
+    return "xor\t%0, %3, %0\;li\t%3, 0";
+  }
   [(set_attr "type" "multi")
    (set_attr "length" "12")])
 
diff --git a/gcc/testsuite/gcc.target/riscv/pr125320.c b/gcc/testsuite/gcc.target/riscv/pr125320.c
new file mode 100644
index 000000000000..2bc33ce0dfa4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr125320.c
@@ -0,0 +1,10 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mabi=lp64d -march=rv64gc_xtheadmemidx -fstack-protector-strong" } */
+
+void __gen_tempname (char *, int, int, int);
+void
+tempnam ()
+{
+  char buf[4096];
+  __gen_tempname (buf, 0, 0, 2);
+}